[3/2] intel/fs: Teach instruction scheduler about GRF bank conflict cycles.

Submitted by Francisco Jerez on Dec. 6, 2017, 8:46 p.m.

Details

Message ID 20171206204605.10834-1-currojerez@riseup.net
State New
Headers show
Series "Series without cover letter" ( rev: 2 ) in Mesa

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Commit Message

Francisco Jerez Dec. 6, 2017, 8:46 p.m.
This should allow the post-RA scheduler to do a slightly better job at
hiding latency in presence of instructions incurring bank conflicts.
The main purpuse of this patch is not to improve performance though,
but to get conflict cycles to show up in shader-db statistics in order
to make sure that regressions in the bank conflict mitigation pass
don't go unnoticed.
---
 src/intel/compiler/brw_fs.h                      |  1 +
 src/intel/compiler/brw_fs_bank_conflicts.cpp     | 19 +++++++++++++++++++
 src/intel/compiler/brw_schedule_instructions.cpp |  5 +++--
 3 files changed, 23 insertions(+), 2 deletions(-)

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diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 6f7351ee506..62b7631a4ac 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -146,6 +146,7 @@  public:
    bool opt_drop_redundant_mov_to_flags();
    bool opt_register_renaming();
    bool opt_bank_conflicts();
+   unsigned bank_conflict_cycles(const fs_inst *inst);
    bool register_coalesce();
    bool compute_to_mrf();
    bool eliminate_find_live_channel();
diff --git a/src/intel/compiler/brw_fs_bank_conflicts.cpp b/src/intel/compiler/brw_fs_bank_conflicts.cpp
index dc88cac744b..6912331f5b0 100644
--- a/src/intel/compiler/brw_fs_bank_conflicts.cpp
+++ b/src/intel/compiler/brw_fs_bank_conflicts.cpp
@@ -891,3 +891,22 @@  fs_visitor::opt_bank_conflicts()
    delete[] constrained;
    return true;
 }
+
+/**
+ * Estimate the number of GRF bank conflict cycles incurred by an instruction.
+ *
+ * Note that this neglects conflict cycles prior to register allocation
+ * because we don't know which bank each VGRF is going to end up aligned to.
+ */
+unsigned
+fs_visitor::bank_conflict_cycles(const fs_inst *inst)
+{
+   if (grf_used && inst->is_3src(devinfo) &&
+       is_grf(inst->src[1]) && is_grf(inst->src[2]) &&
+       bank_of(reg_of(inst->src[1])) == bank_of(reg_of(inst->src[2])) &&
+       !is_conflict_optimized_out(devinfo, inst)) {
+      return DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE);
+   } else {
+      return 0;
+   }
+}
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp
index a1e825c661c..692f7125323 100644
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -1543,10 +1543,11 @@  vec4_instruction_scheduler::choose_instruction_to_schedule()
 int
 fs_instruction_scheduler::issue_time(backend_instruction *inst)
 {
+   const unsigned overhead = v->bank_conflict_cycles((fs_inst *)inst);
    if (is_compressed((fs_inst *)inst))
-      return 4;
+      return 4 + overhead;
    else
-      return 2;
+      return 2 + overhead;
 }
 
 int