[v3] drm/i915: Suppress spurious underruns during modeset on g4x+DP

Submitted by Ville Syrjälä on Dec. 5, 2017, 1:33 p.m.

Details

Message ID 20171205133341.8280-1-ville.syrjala@linux.intel.com
State New
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Series "drm/i915: Suppress spurious underruns during modeset on g4x+DP" ( rev: 3 ) in Intel GFX - Try Bot

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Commit Message

Ville Syrjälä Dec. 5, 2017, 1:33 p.m. 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

g4x DP ports seem to generate spurious underruns around the time the
pipe is being enabled and disabled. To make it easy for ourselves let's
just suppress underruns around the entire modeset sequence regardless
of what outputs we're driving.

And for consistency apply the same treatment to valleyview_crtc_enable()
since so that the vlv/chv crtc enable matches the crtc disable (which
just uses i9xx_crtc_disable()).

v2: Wait for vblank before enabling underrun detection during enable
v3: Double or nothing?

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 40 ++++++++++++++++++++++++++++--------
 1 file changed, 32 insertions(+), 8 deletions(-)

Patch hide | download patch | download mbox 

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1f7e312d0d0d..a3e8ca3df956 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5702,6 +5702,8 @@  static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (WARN_ON(intel_crtc->active))
 		return;
 
+	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+
 	if (intel_crtc_has_dp_encoder(intel_crtc->config))
 		intel_dp_set_m_n(intel_crtc, M1_N1);
 
@@ -5719,8 +5721,6 @@  static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_crtc->active = true;
 
-	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-
 	intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
 
 	if (IS_CHERRYVIEW(dev_priv)) {
@@ -5745,6 +5745,8 @@  static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
 	drm_crtc_vblank_on(crtc);
 
 	intel_encoders_enable(crtc, pipe_config, old_state);
+
+	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 }
 
 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
@@ -5770,6 +5772,12 @@  static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 	if (WARN_ON(intel_crtc->active))
 		return;
 
+	/*
+	 * DP on g4x generates spurious
+	 * underruns during the modeset sequence.
+	 */
+	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+
 	i9xx_set_pll_dividers(intel_crtc);
 
 	if (intel_crtc_has_dp_encoder(intel_crtc->config))
@@ -5782,9 +5790,6 @@  static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_crtc->active = true;
 
-	if (!IS_GEN2(dev_priv))
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
-
 	intel_encoders_pre_enable(crtc, pipe_config, old_state);
 
 	i9xx_enable_pll(intel_crtc, pipe_config);
@@ -5804,6 +5809,19 @@  static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
 	drm_crtc_vblank_on(crtc);
 
 	intel_encoders_enable(crtc, pipe_config, old_state);
+
+	DRM_DEBUG_KMS("pipe %c encoder enable done\n", pipe_name(pipe));
+
+	/* Must wait for vblank to avoid spurious FIFO underruns with g4x+DP */
+	if (intel_crtc_has_dp_encoder(pipe_config)) {
+		intel_wait_for_vblank(dev_priv, pipe);
+		intel_wait_for_vblank(dev_priv, pipe);
+	}
+
+	DRM_DEBUG_KMS("pipe %c underrun reporting enable\n", pipe_name(pipe));
+
+	if (!IS_GEN2(dev_priv))
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 }
 
 static void i9xx_pfit_disable(struct intel_crtc *crtc)
@@ -5831,6 +5849,12 @@  static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	int pipe = intel_crtc->pipe;
 
 	/*
+	 * DP on g4x generates spurious
+	 * underruns during the modeset sequence.
+	 */
+	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
+
+	/*
 	 * On gen2 planes are double buffered but the pipe isn't, so we must
 	 * wait for planes to fully turn off before disabling the pipe.
 	 */
@@ -5859,15 +5883,15 @@  static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
 
 	intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
 
-	if (!IS_GEN2(dev_priv))
-		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-
 	if (!dev_priv->display.initial_watermarks)
 		intel_update_watermarks(intel_crtc);
 
 	/* clock the pipe down to 640x480@60 to potentially save power */
 	if (IS_I830(dev_priv))
 		i830_enable_pipe(dev_priv, pipe);
+
+	if (!IS_GEN2(dev_priv))
+		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 }
 
 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,