[2/2] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

Submitted by Weinan Li on Sept. 28, 2017, 2:47 a.m.

Details

Message ID 1506566870-12878-2-git-send-email-weinan.z.li@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Intel GFX

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Commit Message

Weinan Li Sept. 28, 2017, 2:47 a.m.
Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
the host support this feature, need to check the BIT(3) of caps in PVINFO.

Signed-off-by: Weinan Li <weinan.z.li@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_vgpu.c |  5 +++++
 drivers/gpu/drm/i915/i915_vgpu.h |  1 +
 drivers/gpu/drm/i915/intel_lrc.c | 18 +++++++++++++-----
 3 files changed, 19 insertions(+), 5 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 5fe9f3f..6f713c5 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -86,6 +86,11 @@  bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
 	return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
 }
 
+bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
+{
+	return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;
+}
+
 struct _balloon_info_ {
 	/*
 	 * There are up to 2 regions per mappable/unmappable graphic
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index b72bd29..cec0ec1 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -29,6 +29,7 @@ 
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
 bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv);
 
 int intel_vgt_balloon(struct drm_i915_private *dev_priv);
 void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 955c879..cd2af7b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -136,6 +136,7 @@ 
 #include <drm/drmP.h>
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
+#include "i915_vgpu.h"
 #include "intel_mocs.h"
 
 #define RING_EXECLIST_QFULL		(1 << 0x2)
@@ -664,7 +665,12 @@  static void intel_lrc_irq_handler(unsigned long data)
 			&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
 		unsigned int head, tail;
 
-		/* However GVT emulation depends upon intercepting CSB mmio */
+		/* However GVT-g emulation depends upon host kernel
+		 * implementation, need to check support capbility by reading PV
+		 * INFO before access HWSP. Beside from this, another special
+		 * configuration may also need to force use mmio, like IOMMU
+		 * enabled.
+		 */
 		if (unlikely(engine->csb_use_mmio)) {
 			buf = (u32 * __force)
 				(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
@@ -1780,10 +1786,6 @@  static void execlists_set_default_submission(struct intel_engine_cs *engine)
 
 static bool irq_handler_force_mmio(struct drm_i915_private *i915)
 {
-	/* GVT emulation depends upon intercepting CSB mmio */
-	if (intel_vgpu_active(i915))
-		return true;
-
 	/*
 	 * IOMMU adds unpredictable latency causing the CSB write (from the
 	 * GPU into the HWSP) to only be visible some time after the interrupt
@@ -1792,6 +1794,12 @@  static bool irq_handler_force_mmio(struct drm_i915_private *i915)
 	if (intel_vtd_active())
 		return true;
 
+	/* GVT emulation depends upon host kernel implementation, check
+	 * support capbility by reading PV INFO before access HWSP.
+	 */
+	if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
+		return true;
+
 	return false;
 }