drm/amdgpu/gmc8: SRIOV need to program fb location

Submitted by Deng, Emily on July 14, 2017, 9:40 a.m.

Details

Message ID 1500025235-8478-1-git-send-email-Emily.Deng@amd.com
State New
Headers show
Series "drm/amdgpu/gmc8: SRIOV need to program fb location" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Deng, Emily July 14, 2017, 9:40 a.m.
SRIOV won't do vbios post in guest OS, and the mmMC_VM_FB_LOCATION
is pf and vf copy, so still need to program fb location for SRIOV.

BUG: SWDEV-126629

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 55f8710..43be519 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -433,6 +433,9 @@  static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 	}
 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 
+	if (amdgpu_sriov_vf(adev))
+		gmc_v8_0_mc_stop(adev);
+
 	if (gmc_v8_0_wait_for_idle((void *)adev)) {
 		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 	}
@@ -443,6 +446,17 @@  static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 	       adev->mc.vram_end >> 12);
 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 	       adev->vram_scratch.gpu_addr >> 12);
+
+	if (amdgpu_sriov_vf(adev)) {
+		tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
+		tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
+		WREG32(mmMC_VM_FB_LOCATION, tmp);
+		/* XXX double check these! */
+		WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
+		WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
+		WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
+	}
+
 	WREG32(mmMC_VM_AGP_BASE, 0);
 	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
@@ -450,6 +464,9 @@  static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 	}
 
+	if (amdgpu_sriov_vf(adev))
+		gmc_v8_0_mc_resume(adev);
+
 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 
 	tmp = RREG32(mmHDP_MISC_CNTL);

Comments

On Fri, Jul 14, 2017 at 5:40 AM, Emily Deng <Emily.Deng@amd.com> wrote:
> SRIOV won't do vbios post in guest OS, and the mmMC_VM_FB_LOCATION
> is pf and vf copy, so still need to program fb location for SRIOV.
>
> BUG: SWDEV-126629
>
> Signed-off-by: Emily Deng <Emily.Deng@amd.com>

You may want to update gmc_v8_0_vram_gtt_location() as well since we
read vram_start (base in this function) back from
mmMC_VM_FB_LOCATION which is uninitialized.  I believe the vbios
programs the start to 0xf400000000.


> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 55f8710..43be519 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -433,6 +433,9 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
>         }
>         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
>
> +       if (amdgpu_sriov_vf(adev))
> +               gmc_v8_0_mc_stop(adev);
> +

Do you need mc_stop and mc_resume?  You might want to check if the
registers accessed in those functions are per VF otherwise you might
stop the MC for all VFs.

Alex

>         if (gmc_v8_0_wait_for_idle((void *)adev)) {
>                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
>         }
> @@ -443,6 +446,17 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
>                adev->mc.vram_end >> 12);
>         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
>                adev->vram_scratch.gpu_addr >> 12);
> +
> +       if (amdgpu_sriov_vf(adev)) {
> +               tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
> +               tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
> +               WREG32(mmMC_VM_FB_LOCATION, tmp);
> +               /* XXX double check these! */
> +               WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
> +               WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
> +               WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
> +       }
> +
>         WREG32(mmMC_VM_AGP_BASE, 0);
>         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
>         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
> @@ -450,6 +464,9 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
>                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
>         }
>
> +       if (amdgpu_sriov_vf(adev))
> +               gmc_v8_0_mc_resume(adev);
> +
>         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
>
>         tmp = RREG32(mmHDP_MISC_CNTL);
> --
> 1.9.1
>
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