Regression in amd-staging-4.11

Submitted by Martin Babutzka on July 10, 2017, 11 a.m.

Details

Message ID 932178.77331.1499684449106@mailxchange.de
State New
Headers show
Series "Regression in amd-staging-4.11" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Martin Babutzka July 10, 2017, 11 a.m.
[    16.932] (--) Log file renamed from "/var/log/Xorg.pid-3814.log" to "/var/log/Xorg.0.log"
[    16.933] 
X.Org X Server 1.18.4
Release Date: 2016-07-19
[    16.933] X Protocol Version 11, Revision 0
[    16.933] Build Operating System: Linux 4.4.0-59-generic x86_64 Ubuntu
[    16.933] Current Operating System: Linux MM-THINK 4.11.4+ #1 SMP Thu Jun 8 20:22:22 CEST 2017 x86_64
[    16.933] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-4.11.4+ root=UUID=8ceeee85-b9c7-41ec-8e1c-24eb1d5e089b ro modprobe.blacklist=radeon quiet splash zswap.enabled=1 vt.handoff=7
[    16.933] Build Date: 26 January 2017  12:26:18AM
[    16.933] xorg-server 2:1.18.4-1ubuntu6.1~16.04.1 (For technical support please see http://www.ubuntu.com/support) 
[    16.933] Current version of pixman: 0.33.6
[    16.933] 	Before reporting problems, check http://wiki.x.org
	to make sure that you have the latest version.
[    16.933] Markers: (--) probed, (**) from config file, (==) default setting,
	(++) from command line, (!!) notice, (II) informational,
	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
[    16.933] (==) Log file: "/var/log/Xorg.0.log", Time: Sun Jun 11 18:05:08 2017
[    16.933] (==) Using config directory: "/etc/X11/xorg.conf.d"
[    16.933] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
[    16.933] (==) No Layout section.  Using the first Screen section.
[    16.933] (==) No screen section available. Using defaults.
[    16.933] (**) |-->Screen "Default Screen Section" (0)
[    16.933] (**) |   |-->Monitor "<default monitor>"
[    16.933] (==) No device specified for screen "Default Screen Section".
	Using the first device section listed.
[    16.933] (**) |   |-->Device "Radeon"
[    16.933] (==) No monitor specified for screen "Default Screen Section".
	Using a default monitor configuration.
[    16.933] (==) Automatically adding devices
[    16.933] (==) Automatically enabling devices
[    16.933] (==) Automatically adding GPU devices
[    16.933] (==) Max clients allowed: 256, resource mask: 0x1fffff
[    16.933] (WW) The directory "/usr/share/fonts/X11/cyrillic" does not exist.
[    16.933] 	Entry deleted from font path.
[    16.933] (WW) The directory "/usr/share/fonts/X11/100dpi/" does not exist.
[    16.933] 	Entry deleted from font path.
[    16.933] (WW) The directory "/usr/share/fonts/X11/75dpi/" does not exist.
[    16.933] 	Entry deleted from font path.
[    16.933] (WW) The directory "/usr/share/fonts/X11/100dpi" does not exist.
[    16.933] 	Entry deleted from font path.
[    16.933] (WW) The directory "/usr/share/fonts/X11/75dpi" does not exist.
[    16.933] 	Entry deleted from font path.
[    16.933] (==) FontPath set to:
	/usr/share/fonts/X11/misc,
	/usr/share/fonts/X11/Type1,
	built-ins
[    16.933] (==) ModulePath set to "/usr/lib/x86_64-linux-gnu/xorg/extra-modules,/usr/lib/xorg/extra-modules,/usr/lib/xorg/modules"
[    16.933] (II) The server relies on udev to provide the list of input devices.
	If no devices become available, reconfigure udev or disable AutoAddDevices.
[    16.933] (II) Loader magic: 0x563708360dc0
[    16.933] (II) Module ABI versions:
[    16.933] 	X.Org ANSI C Emulation: 0.4
[    16.933] 	X.Org Video Driver: 20.0
[    16.933] 	X.Org XInput driver : 22.1
[    16.933] 	X.Org Server Extension : 9.0
[    16.934] (++) using VT number 7

[    16.934] (II) systemd-logind: logind integration requires -keeptty and -keeptty was not provided, disabling logind integration
[    16.934] (II) xfree86: Adding drm device (/dev/dri/card0)
[    16.949] (--) PCI:*(0:0:2:0) 8086:0166:17aa:2203 rev 9, Mem @ 0xf0000000/4194304, 0xe0000000/268435456, I/O @ 0x00006000/64, BIOS @ 0x????????/131072
[    16.949] (--) PCI: (0:4:0:0) 1002:6810:1682:7370 rev 0, Mem @ 0xc0000000/268435456, 0xf0c00000/262144, I/O @ 0x00004000/256, BIOS @ 0x????????/131072
[    16.949] (II) LoadModule: "glx"
[    16.949] (II) Loading /usr/lib/xorg/modules/extensions/libglx.so
[    16.950] (II) Module glx: vendor="X.Org Foundation"
[    16.950] 	compiled for 1.18.4, module version = 1.0.0
[    16.950] 	ABI class: X.Org Server Extension, version 9.0
[    16.950] (==) AIGLX enabled
[    16.950] (II) LoadModule: "amdgpu"
[    16.950] (II) Loading /usr/lib/xorg/modules/drivers/amdgpu_drv.so
[    16.950] (II) Module amdgpu: vendor="X.Org Foundation"
[    16.950] 	compiled for 1.18.4, module version = 1.1.2
[    16.950] 	Module class: X.Org Video Driver
[    16.950] 	ABI class: X.Org Video Driver, version 20.0
[    16.950] (II) AMDGPU: Driver for AMD Radeon chipsets: OLAND, OLAND, OLAND, OLAND,
	OLAND, OLAND, OLAND, OLAND, OLAND, OLAND, OLAND, OLAND, OLAND, OLAND,
	OLAND, OLAND, OLAND, HAINAN, HAINAN, HAINAN, HAINAN, HAINAN, HAINAN,
	TAHITI, TAHITI, TAHITI, TAHITI, TAHITI, TAHITI, TAHITI, TAHITI,
	TAHITI, TAHITI, TAHITI, TAHITI, TAHITI, PITCAIRN, PITCAIRN, PITCAIRN,
	PITCAIRN, PITCAIRN, PITCAIRN, PITCAIRN, PITCAIRN, PITCAIRN, PITCAIRN,
	PITCAIRN, PITCAIRN, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE,
	VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE,
	VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, PITCAIRN, BONAIRE,
	BONAIRE, BONAIRE, BONAIRE, BONAIRE, BONAIRE, BONAIRE, BONAIRE,
	BONAIRE, BONAIRE, BONAIRE, KABINI, KABINI, KABINI, KABINI, KABINI,
	KABINI, KABINI, KABINI, KABINI, KABINI, KABINI, KABINI, KABINI,
	KABINI, KABINI, KABINI, MULLINS, MULLINS, MULLINS, MULLINS, MULLINS,
	MULLINS, MULLINS, MULLINS, MULLINS, MULLINS, MULLINS, MULLINS,
	MULLINS, MULLINS, MULLINS, MULLINS, KAVERI, KAVERI, KAVERI, KAVERI,
	KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI,
	KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI,
	KAVERI, KAVERI, HAWAII, HAWAII, HAWAII, HAWAII, HAWAII, HAWAII,
	HAWAII, HAWAII, HAWAII, HAWAII, HAWAII, HAWAII, TOPAZ, TOPAZ, TOPAZ,
	TOPAZ, TOPAZ, TONGA, TONGA, TONGA, TONGA, TONGA, TONGA, TONGA, TONGA,
	TONGA, CARRIZO, CARRIZO, CARRIZO, CARRIZO, CARRIZO, FIJI, STONEY,
	POLARIS11, POLARIS11, POLARIS11, POLARIS11, POLARIS11, POLARIS11,
	POLARIS11, POLARIS11, POLARIS11, POLARIS10, POLARIS10, POLARIS10,
	POLARIS10, POLARIS10, POLARIS10, POLARIS10, POLARIS10, POLARIS10,
	POLARIS10, POLARIS10
[    16.951] (II) [KMS] drm report modesetting isn't supported.
[    16.951] (EE) Screen 0 deleted because of no matching config section.
[    16.951] (II) UnloadModule: "amdgpu"
[    16.951] (EE) Device(s) detected, but none match those in the config file.
[    16.951] (==) Matched modesetting as autoconfigured driver 0
[    16.951] (==) Matched fbdev as autoconfigured driver 1
[    16.951] (==) Matched vesa as autoconfigured driver 2
[    16.951] (==) Assigned the driver to the xf86ConfigLayout
[    16.951] (II) LoadModule: "modesetting"
[    16.951] (II) Loading /usr/lib/xorg/modules/drivers/modesetting_drv.so
[    16.951] (II) Module modesetting: vendor="X.Org Foundation"
[    16.951] 	compiled for 1.18.4, module version = 1.18.4
[    16.951] 	Module class: X.Org Video Driver
[    16.951] 	ABI class: X.Org Video Driver, version 20.0
[    16.951] (II) LoadModule: "fbdev"
[    16.951] (II) Loading /usr/lib/xorg/modules/drivers/fbdev_drv.so
[    16.951] (II) Module fbdev: vendor="X.Org Foundation"
[    16.951] 	compiled for 1.18.4, module version = 0.4.4
[    16.951] 	Module class: X.Org Video Driver
[    16.951] 	ABI class: X.Org Video Driver, version 20.0
[    16.951] (II) LoadModule: "vesa"
[    16.951] (II) Loading /usr/lib/xorg/modules/drivers/vesa_drv.so
[    16.951] (II) Module vesa: vendor="X.Org Foundation"
[    16.951] 	compiled for 1.18.4, module version = 2.3.4
[    16.951] 	Module class: X.Org Video Driver
[    16.951] 	ABI class: X.Org Video Driver, version 20.0
[    16.952] (II) AMDGPU: Driver for AMD Radeon chipsets: OLAND, OLAND, OLAND, OLAND,
	OLAND, OLAND, OLAND, OLAND, OLAND, OLAND, OLAND, OLAND, OLAND, OLAND,
	OLAND, OLAND, OLAND, HAINAN, HAINAN, HAINAN, HAINAN, HAINAN, HAINAN,
	TAHITI, TAHITI, TAHITI, TAHITI, TAHITI, TAHITI, TAHITI, TAHITI,
	TAHITI, TAHITI, TAHITI, TAHITI, TAHITI, PITCAIRN, PITCAIRN, PITCAIRN,
	PITCAIRN, PITCAIRN, PITCAIRN, PITCAIRN, PITCAIRN, PITCAIRN, PITCAIRN,
	PITCAIRN, PITCAIRN, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE,
	VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE,
	VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, VERDE, PITCAIRN, BONAIRE,
	BONAIRE, BONAIRE, BONAIRE, BONAIRE, BONAIRE, BONAIRE, BONAIRE,
	BONAIRE, BONAIRE, BONAIRE, KABINI, KABINI, KABINI, KABINI, KABINI,
	KABINI, KABINI, KABINI, KABINI, KABINI, KABINI, KABINI, KABINI,
	KABINI, KABINI, KABINI, MULLINS, MULLINS, MULLINS, MULLINS, MULLINS,
	MULLINS, MULLINS, MULLINS, MULLINS, MULLINS, MULLINS, MULLINS,
	MULLINS, MULLINS, MULLINS, MULLINS, KAVERI, KAVERI, KAVERI, KAVERI,
	KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI,
	KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI, KAVERI,
	KAVERI, KAVERI, HAWAII, HAWAII, HAWAII, HAWAII, HAWAII, HAWAII,
	HAWAII, HAWAII, HAWAII, HAWAII, HAWAII, HAWAII, TOPAZ, TOPAZ, TOPAZ,
	TOPAZ, TOPAZ, TONGA, TONGA, TONGA, TONGA, TONGA, TONGA, TONGA, TONGA,
	TONGA, CARRIZO, CARRIZO, CARRIZO, CARRIZO, CARRIZO, FIJI, STONEY,
	POLARIS11, POLARIS11, POLARIS11, POLARIS11, POLARIS11, POLARIS11,
	POLARIS11, POLARIS11, POLARIS11, POLARIS10, POLARIS10, POLARIS10,
	POLARIS10, POLARIS10, POLARIS10, POLARIS10, POLARIS10, POLARIS10,
	POLARIS10, POLARIS10
[    16.952] (II) modesetting: Driver for Modesetting Kernel Drivers: kms
[    16.952] (II) FBDEV: driver for framebuffer: fbdev
[    16.952] (II) VESA: driver for VESA chipsets: vesa
[    16.952] (WW) xf86OpenConsole: setpgid failed: Operation not permitted
[    16.952] (WW) xf86OpenConsole: setsid failed: Operation not permitted
[    16.964] (II) modeset(G0): using drv /dev/dri/card0
[    16.964] (II) Loading sub module "fbdevhw"
[    16.964] (II) LoadModule: "fbdevhw"
[    16.964] (II) Loading /usr/lib/xorg/modules/libfbdevhw.so
[    16.964] (II) Module fbdevhw: vendor="X.Org Foundation"
[    16.964] 	compiled for 1.18.4, module version = 0.0.2
[    16.964] 	ABI class: X.Org Video Driver, version 20.0
[    16.964] (**) FBDEV(0): claimed PCI slot 4@0:0:0
[    16.964] (II) FBDEV(0): using default device
[    16.964] (WW) Falling back to old probe method for vesa
[    16.964] (II) FBDEV(0): Creating default Display subsection in Screen section
	"Default Screen Section" for depth/fbbpp 24/32
[    16.964] (==) FBDEV(0): Depth 24, (==) framebuffer bpp 32
[    16.964] (==) FBDEV(0): RGB weight 888
[    16.964] (==) FBDEV(0): Default visual is TrueColor
[    16.964] (==) FBDEV(0): Using gamma correction (1.0, 1.0, 1.0)
[    16.964] (II) FBDEV(0): hardware: inteldrmfb (video memory: 4128kB)
[    16.964] (II) FBDEV(0): checking modes against framebuffer device...
[    16.964] (II) FBDEV(0): checking modes against monitor...
[    16.964] (--) FBDEV(0): Virtual size is 1366x768 (pitch 1366)
[    16.964] (**) FBDEV(0):  Built-in mode "current"
[    16.964] (==) FBDEV(0): DPI set to (96, 96)
[    16.964] (II) Loading sub module "fb"
[    16.964] (II) LoadModule: "fb"
[    16.964] (II) Loading /usr/lib/xorg/modules/libfb.so
[    16.964] (II) Module fb: vendor="X.Org Foundation"
[    16.964] 	compiled for 1.18.4, module version = 1.0.0
[    16.964] 	ABI class: X.Org ANSI C Emulation, version 0.4
[    16.964] (**) FBDEV(0): using shadow framebuffer
[    16.964] (II) Loading sub module "shadow"
[    16.964] (II) LoadModule: "shadow"
[    16.964] (II) Loading /usr/lib/xorg/modules/libshadow.so
[    16.964] (II) Module shadow: vendor="X.Org Foundation"
[    16.964] 	compiled for 1.18.4, module version = 1.1.0
[    16.964] 	ABI class: X.Org ANSI C Emulation, version 0.4
[    16.965] (==) modeset(G0): Depth 24, (==) framebuffer bpp 32
[    16.965] (==) modeset(G0): RGB weight 888
[    16.965] (==) modeset(G0): Default visual is TrueColor
[    16.965] (II) Loading sub module "glamoregl"
[    16.965] (II) LoadModule: "glamoregl"
[    16.965] (II) Loading /usr/lib/xorg/modules/libglamoregl.so
[    16.967] (II) Module glamoregl: vendor="X.Org Foundation"
[    16.967] 	compiled for 1.18.4, module version = 1.0.0
[    16.967] 	ABI class: X.Org ANSI C Emulation, version 0.4
[    16.967] (II) glamor: OpenGL accelerated X.org driver based.
[    16.974] (II) glamor: EGL version 1.4 (DRI2):
[    16.975] (II) modeset(G0): glamor initialized
[    16.975] (II) modeset(G0): Output LVDS-1-1 has no monitor section
[    16.980] (II) modeset(G0): Output VGA-1-1 has no monitor section
[    17.164] (II) modeset(G0): Output HDMI-1-1 has no monitor section
[    17.164] (II) modeset(G0): Output DP-1-1 has no monitor section
[    17.172] (II) modeset(G0): Output HDMI-1-2 has no monitor section
[    17.172] (II) modeset(G0): Output DP-1-2 has no monitor section
[    17.172] (II) modeset(G0): EDID for output LVDS-1-1
[    17.172] (II) modeset(G0): Manufacturer: LGD  Model: 2d8  Serial#: 0
[    17.172] (II) modeset(G0): Year: 2012  Week: 0
[    17.172] (II) modeset(G0): EDID Version: 1.3
[    17.172] (II) modeset(G0): Digital Display Input
[    17.172] (II) modeset(G0): Max Image Size [cm]: horiz.: 28  vert.: 16
[    17.172] (II) modeset(G0): Gamma: 2.20
[    17.172] (II) modeset(G0): DPMS capabilities: StandBy Suspend Off
[    17.172] (II) modeset(G0): Supported color encodings: RGB 4:4:4 YCrCb 4:4:4 
[    17.172] (II) modeset(G0): First detailed timing is preferred mode
[    17.172] (II) modeset(G0): redX: 0.600 redY: 0.355   greenX: 0.334 greenY: 0.559
[    17.172] (II) modeset(G0): blueX: 0.149 blueY: 0.114   whiteX: 0.313 whiteY: 0.329
[    17.172] (II) modeset(G0): Manufacturer's mask: 0
[    17.172] (II) modeset(G0): Supported detailed timing:
[    17.172] (II) modeset(G0): clock: 75.2 MHz   Image Size:  277 x 156 mm
[    17.172] (II) modeset(G0): h_active: 1366  h_sync: 1414  h_sync_end 1478 h_blank_end 1582 h_border: 0
[    17.172] (II) modeset(G0): v_active: 768  v_sync: 772  v_sync_end 779 v_blanking: 792 v_border: 0
[    17.172] (II) modeset(G0):  LG Display
[    17.172] (II) modeset(G0):  LP125WH2-SLB3
[    17.172] (II) modeset(G0): EDID (in hex):
[    17.172] (II) modeset(G0): 	00ffffffffffff0030e4d80200000000
[    17.172] (II) modeset(G0): 	00160103801c1078ea8855995b558f26
[    17.172] (II) modeset(G0): 	1d505400000001010101010101010101
[    17.172] (II) modeset(G0): 	010101010101601d56d8500018303040
[    17.172] (II) modeset(G0): 	4700159c1000001b0000000000000000
[    17.172] (II) modeset(G0): 	00000000000000000000000000fe004c
[    17.172] (II) modeset(G0): 	4720446973706c61790a2020000000fe
[    17.172] (II) modeset(G0): 	004c503132355748322d534c42330059
[    17.173] (II) modeset(G0): Printing probed modes for output LVDS-1-1
[    17.173] (II) modeset(G0): Modeline "1366x768"x60.0   75.20  1366 1414 1478 1582  768 772 779 792 +hsync -vsync (47.5 kHz eP)
[    17.173] (II) modeset(G0): Modeline "1360x768"x59.8   84.75  1360 1432 1568 1776  768 771 781 798 -hsync +vsync (47.7 kHz d)
[    17.173] (II) modeset(G0): Modeline "1360x768"x60.0   72.00  1360 1408 1440 1520  768 771 781 790 +hsync -vsync (47.4 kHz d)
[    17.173] (II) modeset(G0): Modeline "1024x768"x120.1  133.47  1024 1100 1212 1400  768 768 770 794 doublescan -hsync +vsync (95.3 kHz d)
[    17.173] (II) modeset(G0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz d)
[    17.173] (II) modeset(G0): Modeline "960x720"x120.0  117.00  960 1024 1128 1300  720 720 722 750 doublescan -hsync +vsync (90.0 kHz d)
[    17.173] (II) modeset(G0): Modeline "928x696"x120.1  109.15  928 976 1088 1264  696 696 698 719 doublescan -hsync +vsync (86.4 kHz d)
[    17.173] (II) modeset(G0): Modeline "896x672"x120.0  102.40  896 960 1060 1224  672 672 674 697 doublescan -hsync +vsync (83.7 kHz d)
[    17.173] (II) modeset(G0): Modeline "960x600"x120.0   77.00  960 984 1000 1040  600 601 604 617 doublescan +hsync -vsync (74.0 kHz d)
[    17.173] (II) modeset(G0): Modeline "960x540"x120.0   69.25  960 984 1000 1040  540 541 544 555 doublescan +hsync -vsync (66.6 kHz d)
[    17.173] (II) modeset(G0): Modeline "800x600"x120.0   81.00  800 832 928 1080  600 600 602 625 doublescan +hsync +vsync (75.0 kHz d)
[    17.173] (II) modeset(G0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz d)
[    17.173] (II) modeset(G0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz d)
[    17.173] (II) modeset(G0): Modeline "840x525"x120.0   73.12  840 892 980 1120  525 526 529 544 doublescan -hsync +vsync (65.3 kHz d)
[    17.173] (II) modeset(G0): Modeline "840x525"x119.8   59.50  840 864 880 920  525 526 529 540 doublescan +hsync -vsync (64.7 kHz d)
[    17.173] (II) modeset(G0): Modeline "800x512"x120.3   51.56  800 800 828 832  512 512 514 515 doublescan +hsync +vsync (62.0 kHz d)
[    17.173] (II) modeset(G0): Modeline "700x525"x120.0   61.00  700 744 820 940  525 526 532 541 doublescan +hsync +vsync (64.9 kHz d)
[    17.173] (II) modeset(G0): Modeline "640x512"x120.0   54.00  640 664 720 844  512 512 514 533 doublescan +hsync +vsync (64.0 kHz d)
[    17.173] (II) modeset(G0): Modeline "720x450"x119.8   53.25  720 760 836 952  450 451 454 467 doublescan -hsync +vsync (55.9 kHz d)
[    17.173] (II) modeset(G0): Modeline "640x480"x120.0   54.00  640 688 744 900  480 480 482 500 doublescan +hsync +vsync (60.0 kHz d)
[    17.173] (II) modeset(G0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz d)
[    17.173] (II) modeset(G0): Modeline "680x384"x119.6   42.38  680 716 784 888  384 385 390 399 doublescan -hsync +vsync (47.7 kHz d)
[    17.173] (II) modeset(G0): Modeline "680x384"x119.9   36.00  680 704 720 760  384 385 390 395 doublescan +hsync -vsync (47.4 kHz d)
[    17.173] (II) modeset(G0): Modeline "576x432"x120.1   40.81  576 608 668 760  432 432 434 447 doublescan -hsync +vsync (53.7 kHz d)
[    17.173] (II) modeset(G0): Modeline "512x384"x120.0   32.50  512 524 592 672  384 385 388 403 doublescan -hsync -vsync (48.4 kHz d)
[    17.173] (II) modeset(G0): Modeline "400x300"x120.6   20.00  400 420 484 528  300 300 302 314 doublescan +hsync +vsync (37.9 kHz d)
[    17.173] (II) modeset(G0): Modeline "400x300"x112.7   18.00  400 412 448 512  300 300 301 312 doublescan +hsync +vsync (35.2 kHz d)
[    17.173] (II) modeset(G0): Modeline "320x240"x120.1   12.59  320 328 376 400  240 245 246 262 doublescan -hsync -vsync (31.5 kHz d)
[    17.178] (II) modeset(G0): EDID for output VGA-1-1
[    17.360] (II) modeset(G0): EDID for output HDMI-1-1
[    17.360] (II) modeset(G0): EDID for output DP-1-1
[    17.368] (II) modeset(G0): EDID for output HDMI-1-2
[    17.368] (II) modeset(G0): EDID for output DP-1-2
[    17.368] (II) modeset(G0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
[    17.368] (==) modeset(G0): DPI set to (96, 96)
[    17.368] (II) Loading sub module "fb"
[    17.368] (II) LoadModule: "fb"
[    17.368] (II) Loading /usr/lib/xorg/modules/libfb.so
[    17.368] (II) Module fb: vendor="X.Org Foundation"
[    17.368] 	compiled for 1.18.4, module version = 1.0.0
[    17.368] 	ABI class: X.Org ANSI C Emulation, version 0.4
[    17.368] (II) UnloadModule: "vesa"
[    17.368] (II) Unloading vesa
[    17.368] (==) Depth 24 pixmap format is 32 bpp
[    17.425] (==) modeset(G0): Backing store enabled
[    17.425] (==) modeset(G0): Silken mouse enabled
[    17.426] (II) modeset(G0): RandR 1.2 enabled, ignore the following RandR disabled message.
[    17.426] (==) modeset(G0): DPMS enabled
[    17.426] (WW) modeset(G0): Option "DRI" is not used
[    17.426] (WW) modeset(G0): Option "EXAVSync" is not used
[    17.426] (WW) modeset(G0): Option "SwapbuffersWait" is not used
[    17.426] (II) modeset(G0): [DRI2] Setup complete
[    17.426] (II) modeset(G0): [DRI2]   DRI driver: i965
[    17.426] (II) modeset(G0): [DRI2]   VDPAU driver: i965
[    17.667] (==) FBDEV(0): Backing store enabled
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.667] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (EE) FBDEV(0): FBIOPUTCMAP: Device or resource busy
[    17.668] (==) FBDEV(0): DPMS enabled
[    17.668] (--) RandR disabled
[    17.671] (II) SELinux: Disabled on system
[    17.671] (II) AIGLX: Screen 0 is not DRI2 capable
[    17.671] (EE) AIGLX: reverting to software rendering
[    17.681] (II) AIGLX: enabled GLX_MESA_copy_sub_buffer
[    17.681] (II) AIGLX: Loaded and initialized swrast
[    17.682] (II) GLX: Initialized DRISWRAST GL provider for screen 0
[    17.682] (II) modeset(G0): Damage tracking initialized
[    17.682] (EE) 
[    17.682] (EE) Backtrace:
[    17.682] (EE) 0: /usr/lib/xorg/Xorg (xorg_backtrace+0x4e) [0x5637080d4b6e]
[    17.682] (EE) 1: /usr/lib/xorg/Xorg (0x563707f22000+0x1b6ef9) [0x5637080d8ef9]
[    17.682] (EE) 2: /lib/x86_64-linux-gnu/libc.so.6 (0x7fd068d16000+0x354b0) [0x7fd068d4b4b0]
[    17.682] (EE) 3: /usr/lib/xorg/Xorg (RRSetChanged+0x50) [0x563708035be0]
[    17.682] (EE) 4: /usr/lib/xorg/Xorg (RRScreenSetSizeRange+0x54) [0x56370803a424]
[    17.682] (EE) 5: /usr/lib/xorg/Xorg (xf86RandR12CreateScreenResources+0x2c6) [0x563707ff6056]
[    17.682] (EE) 6: /usr/lib/xorg/Xorg (0x563707f22000+0xc6d70) [0x563707fe8d70]
[    17.682] (EE) 7: /usr/lib/xorg/Xorg (0x563707f22000+0x57c3c) [0x563707f79c3c]
[    17.682] (EE) 8: /lib/x86_64-linux-gnu/libc.so.6 (__libc_start_main+0xf0) [0x7fd068d36830]
[    17.682] (EE) 9: /usr/lib/xorg/Xorg (_start+0x29) [0x563707f64049]
[    17.682] (EE) 
[    17.682] (EE) Segmentation fault at address 0xa0
[    17.682] (EE) 
Fatal server error:
[    17.682] (EE) Caught signal 11 (Segmentation fault). Server aborting
[    17.682] (EE) 
[    17.682] (EE) 
Please consult the The X.Org Foundation support 
	 at http://wiki.x.org
 for help. 
[    17.682] (EE) Please also check the log file at "/var/log/Xorg.0.log" for additional information.
[    17.682] (EE) 
[    18.271] (EE) Server terminated with error (1). Closing log file.

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commit cdd8afd871683b14821a12377441c190ec9f9ac7
Merge: d87db1b2c751 931e0fabb75a
Author: Martin Babutzka <martin.babutzka@web.de>
Date:   Thu Jun 8 19:44:44 2017 +0200

    Merge branch 'amd-staging-4.11' of git://people.freedesktop.org/~agd5f/linux into mbab_4.11

commit 931e0fabb75a154c75b9b21aa81a9a3e1ec5d08f
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Fri Jun 2 17:16:31 2017 -0400

    drm/amdgpu: drop deprecated drm_get_pci_dev and drm_put_dev
    
    Open code them so we can adjust the order in the
    driver more easily.
    
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 147b85668c6af4f7481037fe5903d965345cafd1
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Fri Jun 2 16:52:08 2017 -0400

    drm/amdgpu: call pci_[un]register_driver() directly
    
    Rather than calling the deprecated drm_pci_init() and
    drm_pci_exit() which just wrapped the pci functions
    anyway.
    
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 52fa5e2fc4ecb0f2b779a3c4c1d390c93551eb86
Author: Michel Dänzer <michel.daenzer@amd.com>
Date:   Mon May 29 18:05:20 2017 +0900

    drm/amdgpu/radeon: Use radeon by default for CIK GPUs
    
    Even if CONFIG_DRM_AMDGPU_CIK is enabled.
    
    There is no feature parity yet for CIK, in particular amdgpu doesn't
    support HDMI/DisplayPort audio without DC.
    
    v2:
    * Clarify the lack of feature parity being related to HDMI/DP audio.
    * Fix "SI" typo in DRM_AMDGPU_CIK help entry.
    
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>

commit 2cbcfc9900d77b2248c24f0f3332e3f0479a2099
Author: Michel Dänzer <michel.daenzer@amd.com>
Date:   Mon May 29 17:32:38 2017 +0900

    drm/radeon: Make si_support and cik_support parameters always available
    
    This will allow amdgpu-pro / other out-of-tree amdgpu builds to make use
    of these options for using the out-of-tree amdgpu driver instead of the
    in-tree radeon driver in a clean way.
    
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>

commit d2e499e10c42fed9a1502946c55c77ce393d5a11
Author: Felix Kuehling <Felix.Kuehling@amd.com>
Date:   Mon Jun 5 18:57:32 2017 +0900

    drm/amdgpu: Update Kconfig help for SI and CIK support
    
    Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Acked-by: Michel Dänzer <michel.daenzer@amd.com>

commit 70b696cc1961fca375f4eeb649df90d17016fc52
Author: Felix Kuehling <Felix.Kuehling@amd.com>
Date:   Mon Jun 5 18:53:55 2017 +0900

    drm/amdgpu: Add module param to control SI support
    
    If AMDGPU supports SI, add a module parameter to control SI
    support. It's off by default in AMDGPU as long as SI suppost is
    experimental, while it is on by default in radeon.
    
    Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Acked-by: Michel Dänzer <michel.daenzer@amd.com>
    
    [ Michel Dänzer: Squash in amdgpu_si_support initialization fix ]
    Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 6046af54d2a1a3dba6430dcb0a23a17437578804
Author: Felix Kuehling <Felix.Kuehling@amd.com>
Date:   Mon Jun 5 18:52:51 2017 +0900

    drm/radeon: Add module param to control SI support
    
    If AMDGPU supports SI, add a module parameter to control SI
    support in radeon. It's on by default in radeon, while it will be
    off by default in AMDGPU as long as SI support is experimental.
    
    Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Acked-by: Michel Dänzer <michel.daenzer@amd.com>

commit 451d3f6713dd8b2cd0187d44ab560bce006154ff
Author: Felix Kuehling <Felix.Kuehling@amd.com>
Date:   Mon Jun 5 18:43:27 2017 +0900

    drm/amdgpu: Add module param to control CIK support
    
    If AMDGPU supports CIK, add a module parameter to control CIK
    support. It's on by default in AMDGPU, while it is off by default
    in radeon.
    
    Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Acked-by: Michel Dänzer <michel.daenzer@amd.com>

commit 2203d4cc05277a0fe50f56668cf529e92027b72e
Author: Christian König <christian.koenig@amd.com>
Date:   Tue May 16 14:30:27 2017 +0200

    drm/amdgpu: stop joining VM PTE updates
    
    This isn't beneficial any more since VRAM allocations are now split
    so that they fits into a single page table.
    
    Signed-off-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
    Reviewed-by: Chunming Zhou <david1.zhou@amd.com>

commit 8f94be8bef5c18649b720c6282734d1fb957122f
Author: Christian König <christian.koenig@amd.com>
Date:   Mon May 15 15:19:10 2017 +0200

    drm/amdgpu: cache the complete pde
    
    Makes it easier to update the PDE with huge pages.
    
    Signed-off-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
    Reviewed-by: Chunming Zhou <david1.zhou@amd.com>

commit 04a14e09a9249160121bf7534c6d54229486472c
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Wed Jun 7 15:27:52 2017 -0400

    drm/amdgpu/gfx: consolidate mqd buffer setup code
    
    It was duplicated across multiple generations.
    
    Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 61c008b37708c960e5cc6743850776638507e6e6
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Wed Jun 7 14:20:21 2017 -0400

    drm/amdgpu/gfx: move mec parameter setup into sw_init
    
    This will allow us to share more mec code.
    
    Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit c905cd61cf09ab0dce8b6eb1adc58da7e71dcbb4
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Wed Jun 7 13:31:32 2017 -0400

    drm/amdgpu/gfx: move more common KIQ code to amdgpu_gfx.c
    
    Lots more common stuff.
    
    Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit f8b40e07be05278c17b12e575ef5ea6614b8585c
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Wed Jun 7 12:59:29 2017 -0400

    drm/amdgpu: move mec queue helpers to amdgpu_gfx.h
    
    They are gfx related, not general helpers.
    
    Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 3c592b4137b123b2c9416cc20b2bc5abf985d898
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Wed Jun 7 13:09:53 2017 -0400

    drm/amdgpu/gfx9: remove spurious line in kiq setup
    
    This overrode what queue was actually assigned for kiq.
    
    Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit bfcb46646c4b4e15fbdcabc66938806b2e4ab956
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Wed Jun 7 14:22:48 2017 -0400

    drm/amdgpu/gfx8: whitespace change
    
    Make it consistent.
    
    Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit df23e1c1de9e84b73e329dbaf75253bf4282c3cd
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Wed Jun 7 11:07:48 2017 -0400

    drm/amdgpu/gfx9: Raven has two MECs
    
    This was missed when Andres' queue patches were rebased.
    
    Fixes: 42794b27 (drm/amdgpu: take ownership of per-pipe configuration v3)
    Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 96a6b81379781d9d4d1373331ef9d4a8502ec517
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Wed Jun 7 11:05:26 2017 -0400

    drm/amdgpu: move gfx_v*_0_compute_queue_acquire to common code
    
    Same function was duplicated in all gfx IP files.
    
    Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit ff9fa0e001196962da490738def5fd16eaa4da1d
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Wed Jun 7 10:46:06 2017 -0400

    drm/amdgpu: fix mec queue policy on single MEC asics
    
    Fixes hangs on single MEC asics.
    
    Fixes: 2ed286fb434 (drm/amdgpu: new queue policy, take first 2 queues of each pipe v2)
    Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 2da3ceab2b59b61a759d6fbc2739b054f32406c4
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Tue Jun 6 17:41:20 2017 -0400

    drm/amdgpu/gfx: create a common bitmask function (v2)
    
    The same function was duplicated in all the gfx IPs. Use
    a single implementation for all.
    
    v2: use static inline (Alex Xie)
    
    Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
    Suggested-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit b8ef2dd58c974eec5b070b54697e7769891ce4eb
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Wed May 31 10:05:04 2017 -0400

    drm/amdgpu/gfx8: drop per-APU CU limits
    
    Always use the max for the family rather than the per sku limits.
    This makes sure the mask is always the max size to avoid reporting
    the wrong number of CUs.
    
    Reviewed-by: Alex Xie <AlexBin.Xie@amd.com>
    Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
    Cc: stable@vger.kernel.org
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 62f8ddfb6b7aeb8e19eab1d7ce4ff7b4385cd12d
Author: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Date:   Tue Jun 6 23:06:48 2017 +0530

    soc/amd/raven: TDM Mode enablement for 2Ch/4Ch streams
    
    Implemented TDM mode changes to support 2Ch/4ch streams
    and 16/32 bit as container size
    
    Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 68a44c5fa6c119a7e7a4ad498e7dc29ecb55f280
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Fri Jun 2 16:30:46 2017 -0400

    drm/amdgpu/gfx6: properly cache mc_arb_ramcfg
    
    This was missing for gfx6.
    
    Acked-by: Huang Rui <ray.huang@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Cc: stable@vger.kernel.org

commit 380adfcfc75ea789c2629add6c9d1d2ece5a293b
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Mon Jun 5 11:03:59 2017 -0400

    drm/amdgpu/gfx9: new queue policy, take first 2 queues of each pipe
    
    Instead of taking the first pipe and giving the rest to kfd, take the
    first 2 queues of each pipe.
    
    Effectively, amdgpu and amdkfd own the same number of queues. But
    because the queues are spread over multiple pipes the hardware will be
    able to better handle concurrent compute workloads.
    
    amdgpu goes from 1 pipe to 4 pipes, i.e. from 1 compute threads to 4
    amdkfd goes from 3 pipe to 4 pipes, i.e. from 3 compute threads to 4
    
    gfx9 was missed when this patch set was rebased to include gfx9.
    
    Acked-by: Tom St Denis <tom.stdenis@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 80bf9ee118eb57c756bfe7a4d7d6f64bd95f31e1
Author: Alex Deucher <alexander.deucher@amd.com>
Date:   Mon Jun 5 10:58:56 2017 -0400

    drm/amdgpu/gfx9: allocate queues horizontally across pipes
    
    Pipes provide better concurrency than queues, therefore we want to make
    sure that apps use queues from different pipes whenever possible.
    
    Optimize for the trivial case where an app will consume rings in order,
    therefore we don't want adjacent rings to belong to the same pipe.
    
    gfx9 was missed when these patches were rebased.
    
    Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit ecf7b68e60b32a9ac84a26879f824269eb6de192
Author: Hawking Zhang <Hawking.Zhang@amd.com>
Date:   Tue Jun 6 16:25:44 2017 +0800

    drm/amd/powerplay: fix memory leak in cz_hwmgr backend
    
    vddc_dep_on_dal_pwrl is allocated and initialized in cz_hwmgr_backend_init
    Thus free the memory in cz_hwmgr_backend_fini
    
    Change-Id: Idd6dd4b76894579674bf334339b71df8559637fd
    Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit a987bf6d1ca1144d06654d2ef3f48dd7916dc1f1
Author: Hawking Zhang <Hawking.Zhang@amd.com>
Date:   Tue Jun 6 16:19:34 2017 +0800

    drm/amd/powerplay: fix memory leak in rv_hwmgr backend
    
    vddc_dep_on_dal_pwrl and vq_budgeting_table are allocated and initialized
    in rv_hwmgr_backend_init. Thus free the memory in rv_hwmgr_backend_fini
    
    Change-Id: I15878ccb6a39848b764844e45f2ac375164906ad
    Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit bc9f51ac06fccf3dd8fbf6da637f5120394d09ac
Author: Eric Huang <JinHuiEric.Huang@amd.com>
Date:   Fri Jun 2 10:57:24 2017 -0400

    drm/amd/powerplay: add sclk and mclk overdrive for vega10
    
    Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit a76ddaaa53b844f2ef3a01d41eaf23a60de9571f
Author: Rex Zhu <Rex.Zhu@amd.com>
Date:   Fri Jun 2 20:04:40 2017 +0800

    drm/amd/powerplay: fix populate dpm level failed when s3 on vega10.
    
    As the min clk may be  large than boot level can support.
    in this case, just ignore the min clk.
    
    Change-Id: I95863ec5201ce7b2dacc65e4a1c29324bdc43616
    Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit ab25a9e585ca172760fd70b6cdff8a0ce5a3f992
Author: Huang Rui <ray.huang@amd.com>
Date:   Thu Jun 1 15:33:26 2017 +0800

    drm/amdgpu: update to use RREG32_SOC15/WREG32_SOC15 for gmc9
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit bb8c277d9c4eeec45f5b51645eb9aa4c561f4a13
Author: Huang Rui <ray.huang@amd.com>
Date:   Thu Jun 1 15:30:04 2017 +0800

    drm/amdgpu: update to use RREG32_SOC15/WREG32_SOC15 for mmhub
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit 7a72872de9af38ab1df5c6b0c327c2804be163df
Author: Huang Rui <ray.huang@amd.com>
Date:   Thu Jun 1 15:15:28 2017 +0800

    drm/amdgpu: update to use RREG32_SOC15/WREG32_SOC15 for gfxhub
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit 4effc4492020aac862bf550c67f4bdcd8daab8b6
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 10:35:42 2017 +0800

    drm/amdgpu: fix the gart table cleared issue for S3
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Reviewed-by: Christian König <christian.koenig@amd.com>

commit 98fe68e9e0939a7aeb8727af881639abb8cb8c3e
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 3 09:52:06 2017 +0800

    drm/amdgpu: add ip block number prints
    
    User is able to follow the ip block number to write the ip_block_mask for
    selecting the one which user would like to enable.
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit cf13bd3e245b523a914230b9e2bde7045c452c30
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 3 09:40:17 2017 +0800

    drm/amdgpu: add ip name print for selecting ips with ip_block_mask
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit f5e3b9749a2bedaacb14157c9c02523a99082a3c
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 23:49:46 2017 +0800

    drm/amdgpu: remove mmhub ip
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit acbf1d3d082ae79fb47b4e4215ee7acff12f3d97
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 23:46:26 2017 +0800

    drm/amdgpu: remove gfxhub ip
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit 66abc8e4a41ff015339fb77f90b313144cb48a00
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 23:35:44 2017 +0800

    drm/amdgpu: export mmhub get clockgating into gmc
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit 37a498b1cba919bfc58707958e68ab76f66fcf1a
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 23:13:34 2017 +0800

    drm/amdgpu: export mmhub set clockgating into gmc
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit d64f3fb75ccd377d82a4a118c6ed60e6de4858d3
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 22:59:18 2017 +0800

    drm/amdgpu: export mmhub sw_init into gmc
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit 91e2bcd0a58d2216d9d63441fe1af3b3bea1e5fe
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 22:57:18 2017 +0800

    drm/amdgpu: export gfxhub sw_init into gmc
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit 89785b68e5b765944b1e21f041482a191340f56f
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 22:32:35 2017 +0800

    drm/amdgpu: fix to miss program invalidation at resume
    
    This patch moves invalidation into gart enable function from hw_init.
    Because we would like align the sequence calling between init and resume.
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit a116e4c0ed9b90a07ebcab82a6641fabbe39fcf7
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 22:17:11 2017 +0800

    drm/amdgpu: abstract setup vmid config for gfxhub/mmhub
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit ca2f3f13edf4e8e2d0e7eec8b1e9bfa786ec70fc
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 21:52:00 2017 +0800

    drm/amdgpu: abstract disable identity aperture for gfxhub/mmhub
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit 2b2974f34b1d9cf6106ccc1f3a2e19a81385fa1e
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 21:39:10 2017 +0800

    drm/amdgpu: abstract system domain enablement for gfxhub/mmhub
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit 4acc9ebc168feb281627f70e6f72dc9f2910e3a8
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 18:07:48 2017 +0800

    drm/amdgpu: abstract cache initialization for gfxhub/mmhub
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit 0ff2d00b4fa6c3b6ac83a2598e931ad8a13962f3
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 17:19:01 2017 +0800

    drm/amdgpu: abstract TLB initialization for gfxhub/mmhub
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit ca0da0c98c511f5869af667ffdce2f8faa46125f
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 17:04:28 2017 +0800

    drm/amdgpu: abstract system aperture initialization for gfxhub/mmhub
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit a1a58460155b167c6362a88f7d540c778952fe5b
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 16:40:14 2017 +0800

    drm/amdgpu: abstract gart aperture initialization for gfxhub/mmhub
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit 860b07899342223ce6044ae7fd2cec3a0348b089
Author: Huang Rui <ray.huang@amd.com>
Date:   Wed May 31 16:20:48 2017 +0800

    drm/amdgpu: abstract gart table initialization for gfxhub/mmhub
    
    Signed-off-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>

commit c6795aaac6be621964c359c42b911f108e04ecc9
Author: Leo Liu <leo.liu@amd.com>
Date:   Wed May 31 14:25:54 2017 -0400

    drm/amdgpu: add saved_bo to save vce 4.0 context when suspend
    
    We are using PSP to resume firmware after suspend, and it is
    resumed at where it got suspended, so we'd better save the
    the context.
    
    Signed-off-by: Leo Liu <leo.liu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 0b9f7966f35e655c958c03f173c05c346a89f5d2
Author: Leo Liu <leo.liu@amd.com>
Date:   Wed May 31 14:13:20 2017 -0400

    drm/amdgpu: use existing function amdgpu_bo_create_kernel
    
    To simplify vce bo create
    
    Signed-off-by: Leo Liu <leo.liu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit fafdc647f3ceddd971d4d5270a0b822e233a803d
Author: Leo Liu <leo.liu@amd.com>
Date:   Wed May 31 14:07:36 2017 -0400

    drm/amdgpu: add vcpu_bo cpu address for vce
    
    Signed-off-by: Leo Liu <leo.liu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit b79f587ef1e7672f2f388ac2afdd35f84b9d41fd
Author: Alex Xie <AlexBin.Xie@amd.com>
Date:   Thu Jun 1 09:42:59 2017 -0400

    drm/amdgpu: Move compute vm bug logic to amdgpu_vm.c
    
      In review, Christian would like to keep the logic
      inside amdgpu_vm.c with a cost of slightly slower.
      The loop is still optimized out with this patch.
    
    v2: remove the if statement. Now it is not slower.
    
    Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
    Reviewed-by: Christian König <christian.koeng@amd.com>

commit f9d4ad3814461556ea04324d052fa41794e5ac94
Author: Rex Zhu <Rex.Zhu@amd.com>
Date:   Wed May 31 19:53:04 2017 +0800

    drm/amd/powerplay: enable CKS by default on vega10.
    
    Change-Id: I4af08729b339d016d8afe13b6e44cb7a83cb72da
    Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 9b0f83cdf3b28e8d87a0f1e044a01020e91f18bb
Author: Rex Zhu <Rex.Zhu@amd.com>
Date:   Wed May 31 19:29:53 2017 +0800

    drm/amd/powerplay: Align with VBIOS to support AVFS parameters.
    
    Change-Id: Ib20906310d22686e07f946b6666777e59195b49f
    Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 1e1877f6839676d4eb2f88953e669b6ed25f4f42
Author: Rex Zhu <Rex.Zhu@amd.com>
Date:   Wed May 31 16:58:31 2017 +0800

    drm/amd/powerplay: Add floor DCEF for DS on boot.
    
    Use the vbios to look up the default frequencies
    for socclk and dcefclk.
    
    Change-Id: I665a23cd625b206f2ae24cb8da009c59eaf513fb
    Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 294b7c2b81a60b252c6c34b565f5a9d9d1c055a8
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Fri Mar 17 14:41:21 2017 -0400

    drm/amdgpu: use LRU mapping policy for SDMA engines
    
    Spreading the load across multiple SDMA engines can increase memory
    transfer performance.
    
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit b134f016c3bf296428e98db5452f773583d27025
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Fri Mar 17 14:30:15 2017 -0400

    drm/amdgpu: guarantee bijective mapping of ring ids for LRU v3
    
    Depending on usage patterns, the current LRU policy may create a
    non-injective mapping between userspace ring ids and kernel rings.
    
    This behaviour is undesired as apps that attempt to fill all HW blocks
    would be unable to reach some of them.
    
    This change forces the LRU policy to create bijective mappings only.
    
    v2: compress ring_blacklist
    v3: simplify amdgpu_ring_is_blacklisted() logic
    
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 5c784187e704a507cc25ccccb8cc18ea82ac0e8a
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Mon Mar 6 16:27:55 2017 -0500

    drm/amdgpu: implement lru amdgpu_queue_mgr policy for compute v4
    
    Use an LRU policy to map usermode rings to HW compute queues.
    
    Most compute clients use one queue, and usually the first queue
    available. This results in poor pipe/queue work distribution when
    multiple compute apps are running. In most cases pipe 0 queue 0 is
    the only queue that gets used.
    
    In order to better distribute work across multiple HW queues, we adopt
    a policy to map the usermode ring ids to the LRU HW queue.
    
    This fixes a large majority of multi-app compute workloads sharing the
    same HW queue, even though 7 other queues are available.
    
    v2: use ring->funcs->type instead of ring->hw_ip
    v3: remove amdgpu_queue_mapper_funcs
    v4: change ring_lru_list_lock to spinlock, grab only once in lru_get()
    
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 4fc400956852bc2fd470d0e0fc2a9f94f81727a9
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Thu Feb 16 00:47:32 2017 -0500

    drm/amdgpu: untie user ring ids from kernel ring ids v6
    
    Add amdgpu_queue_mgr, a mechanism that allows disjointing usermode's
    ring ids from the kernel's ring ids.
    
    The queue manager maintains a per-file descriptor map of user ring ids
    to amdgpu_ring pointers. Once a map is created it is permanent (this is
    required to maintain FIFO execution guarantees for a context's ring).
    
    Different queue map policies can be configured for each HW IP.
    Currently all HW IPs use the identity mapper, i.e. kernel ring id is
    equal to the user ring id.
    
    The purpose of this mechanism is to distribute the load across multiple
    queues more effectively for HW IPs that support multiple rings.
    Userspace clients are unable to check whether a specific resource is in
    use by a different client. Therefore, it is up to the kernel driver to
    make the optimal choice.
    
    v2: remove amdgpu_queue_mapper_funcs
    v3: made amdgpu_queue_mgr per context instead of per-fd
    v4: add context_put on error paths
    v5: rebase and include new IPs UVD_ENC & VCN_*
    v6: drop unused amdgpu_ring_is_valid_index (Alex)
    
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 8e9ef4a53253351afa8232720448eed85ef01ac0
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Fri Feb 24 20:50:20 2017 -0500

    drm/amdgpu: workaround tonga HW bug in HQD programming sequence
    
    Tonga based asics may experience hangs when an HQD's EOP parameters
    are modified.
    
    Workaround this HW issue by avoiding writes to these registers for
    tonga asics.
    
    Based on the following ROCm commit:
    2a0fb8 - drm/amdgpu: Synchronize KFD HQD load protocol with CP scheduler
    
    From the ROCm git repository:
    https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver.git
    
    CC: Jay Cornwall <Jay.Cornwall@amd.com>
    Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 4a224eab0d69e463bc8414d21fd7e59fe59ac262
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Fri Feb 24 15:28:43 2017 -0500

    drm/amdgpu: condense mqd programming sequence
    
    The MQD structure matches the reg layout. Take advantage of this to
    simplify HQD programming.
    
    Note that the ACTIVE field still needs to be programmed last.
    
    Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 2ed286fb434945658a7ca5eb4b6eda71d95377a1
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Fri Feb 3 23:30:04 2017 -0500

    drm/amdgpu: new queue policy, take first 2 queues of each pipe v2
    
    Instead of taking the first pipe and giving the rest to kfd, take the
    first 2 queues of each pipe.
    
    Effectively, amdgpu and amdkfd own the same number of queues. But
    because the queues are spread over multiple pipes the hardware will be
    able to better handle concurrent compute workloads.
    
    amdgpu goes from 1 pipe to 4 pipes, i.e. from 1 compute threads to 4
    amdkfd goes from 3 pipe to 4 pipes, i.e. from 3 compute threads to 4
    
    v2: fix policy comment
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 3c1c086abb0f027352b23d0cd994d0e61d4c55bd
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Thu Apr 6 00:10:53 2017 -0400

    drm/amdgpu: avoid KIQ clashing with compute or KFD queues v2
    
    Instead of picking an arbitrary queue for KIQ, search for one according
    to policy. The queue must be unused.
    
    Also report the KIQ as an unavailable resource to KFD.
    
    In testing I ran into KCQ initialization issues when using pipes 2/3 of
    MEC2 for the KIQ. Therefore the policy disallows grabbing one of these.
    
    v2: fix (ring.me + 1) to (ring.me -1) in amdgpu_amdkfd_device_init
    
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 8f052a9a941e73e26736c3630687c08d94c5ce0e
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Tue Apr 4 17:18:28 2017 -0400

    drm/amdgpu: remove hardcoded queue_mask in PACKET3_SET_RESOURCES
    
    The assumption that we are only using the first pipe no longer holds.
    Instead, calculate the queue_mask from the queue_bitmap.
    
    Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 72d22da06664757416f6b523087a77032da00c29
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Fri Feb 3 17:31:38 2017 -0500

    drm/amdgpu: allocate queues horizontally across pipes
    
    Pipes provide better concurrency than queues, therefore we want to make
    sure that apps use queues from different pipes whenever possible.
    
    Optimize for the trivial case where an app will consume rings in order,
    therefore we don't want adjacent rings to belong to the same pipe.
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit bd0c8dd841e7386061dd4bc888222a7a7d6eae7a
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Thu Feb 2 15:14:14 2017 -0500

    drm/amdgpu: remove duplicate magic constants from amdgpu_amdkfd_gfx*.c
    
    This information is already available in adev.
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 9012b786240f2634daa32dbe934705d6aa730f9f
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Fri Feb 3 16:28:48 2017 -0500

    drm/amdkfd: allow split HQD on per-queue granularity v5
    
    Update the KGD to KFD interface to allow sharing pipes with queue
    granularity instead of pipe granularity.
    
    This allows for more interesting pipe/queue splits.
    
    v2: fix overflow check for res.queue_mask
    v3: fix shift overflow when setting res.queue_mask
    v4: fix comment in is_pipeline_enabled()
    v5: clamp res.queue_mask to the first MEC only
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 7aed9e90a87b29548c111a40912129b4be4cfe23
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Thu Feb 9 17:39:52 2017 -0500

    drm/amdgpu: teach amdgpu how to enable interrupts for any pipe v3
    
    The current implementation is hardcoded to enable ME1/PIPE0 interrupts
    only.
    
    This patch allows amdgpu to enable interrupts for any pipe of ME1.
    
    v2: added gfx9 support
    v3: use soc15_grbm_select for gfx9
    
    Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 83866f0fc72017d55f40cbd4160cd1e42a2cc3a8
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Thu Feb 2 00:38:22 2017 -0500

    drm/amdgpu: allow split of queues with kfd at queue granularity v4
    
    Previously the queue/pipe split with kfd operated with pipe
    granularity. This patch allows amdgpu to take ownership of an arbitrary
    set of queues.
    
    It also consolidates the last few magic numbers in the compute
    initialization process into mec_init.
    
    v2: support for gfx9
    v3: renamed AMDGPU_MAX_QUEUES to AMDGPU_MAX_COMPUTE_QUEUES
    v4: fix off-by-one in num_mec checks in *_compute_queue_acquire
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 6a399624833a6ca6f37b9a6a254614484d12b1ca
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Wed Feb 1 19:08:23 2017 -0500

    drm/amdgpu: take ownership of per-pipe configuration v3
    
    Make amdgpu the owner of all per-pipe state of the HQDs.
    
    This change will allow us to split the queues between kfd and amdgpu
    with a queue granularity instead of pipe granularity.
    
    This patch fixes kfd allocating an HDP_EOP region for its 3 pipes which
    goes unused.
    
    v2: support for gfx9
    v3: fix gfx7 HPD intitialization
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit b27a5c43df91a6a76c405d83f9630de496869bc2
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Fri Feb 3 16:17:15 2017 -0500

    drm/radeon: take ownership of pipe initialization
    
    Take ownership of pipe initialization away from KFD.
    
    Note that hpd_eop_gpu_addr was already large enough to accomodate all
    pipes.
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 7568dedf2abe9e69419b1ff27262e71e35ce2a13
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Wed Feb 1 17:02:13 2017 -0500

    drm/amdgpu: rename rdev to adev
    
    Rename straggler instances of r(adeon)dev to a(mdgpu)dev
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Acked-by: Christian König <christian.koenig@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit e5a94e55a732f5b5cd5ec90be0b565928f407ede
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Thu Apr 13 13:55:41 2017 -0400

    drm/amdgpu: fix kgd_hqd_load failing to update shadow_wptr
    
    The return value from copy_form_user is 0 for the success case.
    
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit ab58326b1084893c132e61dd10932de1cf05998e
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Wed Feb 1 16:37:42 2017 -0500

    drm/amdgpu: unify MQD programming sequence for kfd and amdgpu v2
    
    Use the same gfx_*_mqd_commit function for kfd and amdgpu codepaths.
    
    This removes the last duplicates of this programming sequence.
    
    v2: fix cp_hqd_pq_wptr value
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Acked-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit af7f22d38a0aaca4b95c8bead14e9f73318a0b31
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Wed Feb 1 16:28:56 2017 -0500

    drm/amdgpu: remove duplicate definition of cik_mqd
    
    The gfxv7 contains a slightly different version of cik_mqd called
    bonaire_mqd. This can introduce subtle bugs if fixes are not applied in
    both places.
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Acked-by: Christian König <christian.koenig@amd.com>
    Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 49822ee7aa1fd2b9f965f7b0a8de185b74e9f89c
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Wed Feb 1 00:01:46 2017 -0500

    drm/amdgpu: detect timeout error when deactivating hqd
    
    Handle HQD deactivation timeouts instead of ignoring them.
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Acked-by: Christian König <christian.koenig@amd.com>
    Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit f2b32f70c75db9d9ae0ad4889bb68344a7d43648
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Wed Apr 12 17:19:54 2017 -0400

    drm/amdgpu: refactor MQD/HQD initialization v3
    
    The MQD programming sequence currently exists in 3 different places.
    Refactor it to absorb all the duplicates.
    
    The success path remains mostly identical except for a slightly
    different order in the non-kiq case. This shouldn't matter if the HQD
    is disabled.
    
    The error handling paths have been updated to deal with the new code
    structure.
    
    v2: the non-kiq path for gfxv8 was dropped in the rebase
    v3: split MEC_HPD_SIZE rename, dropped doorbell changes
    
    Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
    Acked-by: Christian König <christian.koenig@amd.com>
    Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit a18fa34a815a089b51a1422b1375fd6a093b7f4a
Author: Andres Rodriguez <andresx7@gmail.com>
Date:   Wed Apr 12 16:53:50 2017 -0400

    drm/amdgpu: clarify MEC_HPD_SIZE is specific to a gfx generation
    
    Rename MEC_HPD_SIZE to GFXN_MEC_HPD_SIZE to clarify it is specific to a
    gfx generation.
    
    Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

commit 709661f151d9e05936260c52ede39ce103562b39
Author: Rex Zhu <Rex.Zhu@amd.com>
Date:   Sat May 27 18:18:39 2017 +0800

    drm/amd/powerplay: code clean up in vega10_hwmgr.c
    
    Change-Id: I72537f7de3432de6deefc71ae2ac2589a475649d
    Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 9c715927d6268f5e5ef82759cb95addf2657e448
Author: Rex Zhu <Rex.Zhu@amd.com>
Date:   Sat May 27 18:08:13 2017 +0800

    Revert "drm/amd/powerplay: disable engine spread spectrum feature on Vega10."
    
    This reverts commit f8fdaa0e7b81698ba2ad8c2d20c7f9a44c75e0c6.
    firmware add support for this feature, so still ctrl by vbios.
    
    Change-Id: Iab52083396060146380a1fbfd46e5956d63aac92

commit b098f3439e1ee111a19aae1df5138b0ac906c832
Author: Rex Zhu <Rex.Zhu@amd.com>
Date:   Sat May 27 18:05:35 2017 +0800

    drm/amd/powerplay: enable deep sleep by default for vega10
    
    Change-Id: Ie5e7ac76a402ea07dd4a81744df7db67d3704a34
    Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 2a7840d1cc1dd856cce8a3b6ff898c10cf7a47d1
Author: Rex Zhu <Rex.Zhu@amd.com>
Date:   Sat May 27 17:54:08 2017 +0800

    drm/amd/powerplay: enable ulv feature by default for vega10.
    
    Change-Id: I3e4d5ef148f81a8d1b86753482047dd2619490bc
    Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit a3d2285360c071bd7dbdb5aced30365d3fa73e4e
Author: Christian König <christian.koenig@amd.com>
Date:   Tue May 16 14:30:27 2017 +0200

    drm/amdgpu: stop joining VM PTE updates
    
    This isn't beneficial any more since VRAM allocations are now split
    so that they fits into a single page table.
    
    Signed-off-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
    Reviewed-by: Chunming Zhou <david1.zhou@amd.com>

commit d0296222278903b9052aae0f94ce5f07a351a862
Author: Christian König <christian.koenig@amd.com>
Date:   Mon May 15 15:19:10 2017 +0200

    drm/amdgpu: cache the complete pde
    
    Makes it easier to update the PDE with huge pages.
    
    Signed-off-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
    Reviewed-by: Chunming Zhou <david1.zhou@amd.com>

commit 4202b16de8d0c92667eb1de85641fc0250a62c9b
Author: Alex Xie <AlexBin.Xie@amd.com>
Date:   Tue May 30 23:50:10 2017 -0400

    drm/amdgpu: Remove two ! operations in an if condition
    
     Make the code easier to understand.
    
    Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
    Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
    Reviewed-by: Chunming Zhou <david1.zhou@amd.com>

commit 8fe7777062dfc876817fd256ead036bbcdb98b56
Author: Alex Xie <AlexBin.Xie@amd.com>
Date:   Tue May 30 17:10:16 2017 -0400

    drm/amdgpu: Optimize a function called by every IB sheduling
    
      Move several if statements and a loop statment from
      run time to initialization time.
    
    Signed-off-by: Alex Xie <AlexBin.Xie@amd.com>
    Reviewed-by: Chunming Zhou <david1.zhou@amd.com>

commit 17f7e29bd0870fd0f43ba1acde3c6c1b65aee734
Author: Leo Liu <leo.liu@amd.com>
Date:   Mon May 29 13:13:59 2017 -0400

    drm/amdgpu: Program ring for vce instance 1 at its register space
    
    We need program ring buffer on instance 1 register space domain,
    when only if instance 1 available, with two instances or instance 0,
    and we need only program instance 0 regsiter space domain for ring.
    
    Signed-off-by: Leo Liu <leo.liu@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Cc: stable@vger.kernel.org

commit e6a5195f645d3282ab74c2108cdbd57c60562cbc
Author: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Date:   Thu May 11 22:39:31 2017 -0400

    drm/amdgpu: Return EINVAL if no PT BO
    
    This change is also useful for the upcoming changes where page tables
    can be updated by CPU.
    
    Change-Id: I07510ed60c94cf1944ee96bb4b16c40ec88ea17c
    Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
    Reviewed-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

commit 67e18ab8c94e9397ec1a4d7ae509c4153d25938d
Author: Christian König <christian.koenig@amd.com>
Date:   Fri May 12 16:09:26 2017 +0200

    drm/amdgpu: add some extra VM error handling
    
    If updating the PDs fails we now invalidate all entries to try again later.
    
    Signed-off-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
    Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

commit d721a8d7b0a3c41633bcd7dcf63b0837c86bdc55
Author: Christian König <christian.koenig@amd.com>
Date:   Fri May 12 15:39:39 2017 +0200

    drm/amdgpu: cleanup adjust_mc_addr handling v4
    
    Rename adjust_mc_addr to get_vm_pde and check the address bits in one place.
    
    v2: handle vcn as well, keep setting the valid bit manually,
        add a BUG_ON() for GMC v6, v7 and v8 as well.
    v3: handle vcn_v1_0_enc_ring_emit_vm_flush as well.
    v4: fix the BUG_ON mask for GFX6-8
    
    Signed-off-by: Christian König <christian.koenig@amd.com>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>

commit aa7d5b4ec8b924d6d818383a208535ebe22686c5
Author: Hawking Zhang <Hawking.Zhang@amd.com>
Date:   Fri May 26 14:40:36 2017 +0800

    drm/amdgpu: enable lbpw on raven
    
    Change-Id: I131196ac1833cd259fa05e0e5bfe1fc32eb6e6ec
    Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 6ba5fcd473d0bb0caab6d9765891d52368139ff4
Author: Hawking Zhang <Hawking.Zhang@amd.com>
Date:   Fri May 26 14:26:51 2017 +0800

    drm/amdgpu: init lbpw on raven
    
    Load Balancing Per Watt (LBPW) allows dynamically disable CUs
    when they are idle
    
    Change-Id: I05471619ccbae61c5a66ed5dc3c63665fbb81648
    Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit bfc3c327f45a72cfea19333c82d3876bcd0726a6
Author: Hawking Zhang <Hawking.Zhang@amd.com>
Date:   Thu May 25 15:23:49 2017 +0800

    drm/amdgpu: update sdma 4.1 raven specific golden settings
    
    Change-Id: I5c3342ff726789ddc8b64976042dd50e9e90b3a5
    Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 252b6fdc13ab61f2f45d839b1d7d7a1a2aa15b2c
Author: Hawking Zhang <Hawking.Zhang@amd.com>
Date:   Thu May 25 14:58:14 2017 +0800

    drm/amdgpu: update GC 9.1 raven specific golden settings
    
    Change-Id: I4b80cb3e97aba6c1746a9b01310e623656cae3ba
    Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 3ffeacf8dbcacf61fd1e44832944fb3178b27a5d
Author: Hawking Zhang <Hawking.Zhang@amd.com>
Date:   Thu May 25 14:52:44 2017 +0800

    drm/amdgpu: update GC 9.1 golden settings
    
    Change-Id: Ie6be54b099b2f1936803f4cc3cfe52231b64991d
    Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 8d57ffeb6385334ee7e3b9056656100a1a81e5ce
Author: Hawking Zhang <Hawking.Zhang@amd.com>
Date:   Thu May 25 16:15:10 2017 +0800

    drm/amdgpu: remove unnecessary debug message
    
    Change-Id: Ib7599d88d58a776f0edf49f20e4dad752ef05aea
    Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

commit 34b8080714b302d08420b696e1230a69b379dc0d
Author: Eric Huang <JinHuiEric.Huang@amd.com>
Date:   Thu May 25 15:59:59 2017 -0400

    drm/amd/powerplay: fix set tools address for Vega10
    
    Tools fb address was failed to send to smu when smu
    was not running. Changing sequence will fix it.
    
    Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
    Acked-by: Alex Deucher <alexander.deucher@amd.com>

commit 9552c2e7cfde0d3def1c1ac8eab5e57ca80f348b
Author: Eric Huang <JinHuiEric.Huang@amd.com>
Date:   Thu May 25 15:50:30 2017 -0400

    drm/amd/powerplay: fix soft pptable size for Vega10
    
    It is to fix bug of sysfs entry pp_table which had size 0 of output before.
    
    Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
    Acked-by: Alex Deucher <alexander.deucher@amd.com>

commit aac8d29b02cac33d9dc46c4b714c77ae6c9dc353
Author: Shirish S <shirish.s@amd.com>
Date:   Thu May 25 10:05:25 2017 +0530

    drm/amdgpu: optimize amdgpu driver load & resume time
    
    amdgpu_device_resume() & amdgpu_device_init() have a high
    time consuming call of amdgpu_late_init() which sets the
    clock_gating state of all IP blocks and is blocking.
    This patch defers only this setting of clock gating state
    operation to post resume of amdgpu driver but ideally before
    the UI comes up or in some cases post ui as well.
    
    With this change the resume time of amdgpu_device comes down
    from 1.299s to 0.199s which further helps in reducing the overall
    system resume time.
    
    V1: made the optimization applicable during driver load as well.
    
    TEST:(For ChromiumOS on STONEY only)
    * UI comes up
    * amdgpu_late_init() call gets called consistently and no errors reported.
    
    Change-Id: I6cc2817099793b394b382ca706185412a4456f5a
    Signed-off-by: Shirish S <shirish.s@amd.com>
    Reviewed-by: Huang Rui <ray.huang@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Comments

Thanks for the info, is it possible to provide dmesg log for this issue ?


On 07/10/2017 07:00 AM, Martin Babutzka wrote:
>
> Dear AMD graphics developers,
>
> I am one of the guys that regularly builds your amd-staging kernels and
> makes them available for the lazier people. By this we get a nice
> preview of DAL/DC and you get some free beta-testers.
>
> One of the users describe a regression here:
> https://github.com/M-Bab/linux-kernel-amdgpu-binaries/issues/8
>
> Unfortunately the bug details are limited but I can give some
> additional information to pin the bug down:
> All kernels <= 4.11.3+ (merged with amd-staging-4.11 at Fri May 26
> 18:19:03 2017 +0200) are reported to be working and the regression was
> introduced with the kernels >= 4.11.4+ (merged with amd-staging-4.11 at
> Thu Jun 8 19:44:44 2017 +0200). I attached a list of your commits that
> were merged in this time range. The other attachment is an X.org log
> with the trace when amdgpu should be loaded to run a R7 370 GPU.
> The kernel based on amd-staging-4.9 is not affected.
>
> I hope this helps you to find the regression. Just tell me if I can
> provide further details or testing.
>
> Kind regards,
> Martin Babutzka
>
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
On 10/07/17 08:00 PM, Martin Babutzka wrote:
> Dear AMD graphics developers,
> 
> I am one of the guys that regularly builds your amd-staging kernels and
> makes them available for the lazier people. By this we get a nice
> preview of DAL/DC and you get some free beta-testers.
> 
> One of the users describe a regression here:
> https://github.com/M-Bab/linux-kernel-amdgpu-binaries/issues/8
> 
> Unfortunately the bug details are limited but I can give some
> additional information to pin the bug down:
> All kernels <= 4.11.3+ (merged with amd-staging-4.11 at Fri May 26
> 18:19:03 2017 +0200) are reported to be working and the regression was
> introduced with the kernels >= 4.11.4+ (merged with amd-staging-4.11 at
> Thu Jun 8 19:44:44 2017 +0200). I attached a list of your commits that
> were merged in this time range. The other attachment is an X.org log
> with the trace when amdgpu should be loaded to run a R7 370 GPU.

The user probably needs to specify

amdgpu.si_support=1 radeon.si_support=0

(instead of blacklisting the radeon driver) to choose the amdgpu kernel
driver for their GPU.