[0/3] MOCS versioning

Submitted by Ben Widawsky on July 6, 2017, 11:27 p.m.

Details

Message ID 20170706232703.14229-1-ben@bwidawsk.net
State New
Headers show
Series "MOCS versioning" ( rev: 1 ) in Intel GFX

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diff --git a/src/mesa/drivers/dri/i965/brw_mocs.c b/src/mesa/drivers/dri/i965/brw_mocs.c
index 5df154eb86..b7bfdab671 100644
--- a/src/mesa/drivers/dri/i965/brw_mocs.c
+++ b/src/mesa/drivers/dri/i965/brw_mocs.c
@@ -14,6 +14,9 @@ 
 /* Skylake: MOCS is now an index into an array of 62 different caching
  * configurations programmed by the kernel.
  */
+
+/* TC=PTE, LeCC=PTE, LRUM=3, L3CC=WB */
+#define SKL_MOCS_PTE_PTE (3 << 1)
 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
 #define SKL_MOCS_WB  (2 << 1)
 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
@@ -26,6 +29,9 @@  brw_mocs_get_control_state(const struct brw_context *brw,
    switch (brw->gen) {
    default:
    case 9:
+      if (brw->intelScreen->mocs_version > 1)
+         return SKL_MOCS_PTE_PTE;
+
       return type == INTEL_MOCS_PTE ? SKL_MOCS_PTE : SKL_MOCS_WB;
    case 8:
       return type == INTEL_MOCS_PTE ? BDW_MOCS_PTE : BDW_MOCS_WB;