[03/12] drm/amdgpu: Enable SDMA context switching for CIK

Submitted by Zhou, David(ChunMing) on July 4, 2017, 3:07 a.m.

Details

Message ID MWHPR1201MB0206E7CBC52C4399E945EC0FB4D70@MWHPR1201MB0206.namprd12.prod.outlook.com
State New
Headers show
Series "Patches from amd-kfd-staging" ( rev: 4 3 ) in AMD X.Org drivers

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Commit Message

Zhou, David(ChunMing) July 4, 2017, 3:07 a.m.
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>


-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Felix Kuehling

Sent: Tuesday, July 04, 2017 5:11 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix <Felix.Kuehling@amd.com>
Subject: [PATCH 03/12] drm/amdgpu: Enable SDMA context switching for CIK

Enable SDMA context switching on CIK (copied from sdma_v3_0.c).

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>

---
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

 
 	/* halt the engine before programing */
 	cik_sdma_enable(adev, false);
+	/* enable sdma ring preemption */
+	cik_ctx_switch_enable(adev, true);
 
 	/* start the gfx rings and rlc compute queues */
 	r = cik_sdma_gfx_resume(adev);
@@ -984,6 +1013,7 @@ static int cik_sdma_hw_fini(void *handle)  {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+	cik_ctx_switch_enable(adev, false);
 	cik_sdma_enable(adev, false);
 
 	return 0;
--
1.9.1

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diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index c216e16..4a9cea0 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -342,6 +342,33 @@  static void cik_sdma_rlc_stop(struct amdgpu_device *adev)  }
 
 /**
+ * cik_ctx_switch_enable - stop the async dma engines context switch
+ *
+ * @adev: amdgpu_device pointer
+ * @enable: enable/disable the DMA MEs context switch.
+ *
+ * Halt or unhalt the async dma engines context switch (VI).
+ */
+static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool 
+enable) {
+	u32 f32_cntl;
+	int i;
+
+	for (i = 0; i < adev->sdma.num_instances; i++) {
+		f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
+		if (enable) {
+			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
+					AUTO_CTXSW_ENABLE, 1);
+		} else {
+			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
+					AUTO_CTXSW_ENABLE, 0);
+		}
+
+		WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
+	}
+}
+
+/**
  * cik_sdma_enable - stop the async dma engines
  *
  * @adev: amdgpu_device pointer
@@ -537,6 +564,8 @@  static int cik_sdma_start(struct amdgpu_device *adev)