drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle

Submitted by Michel Thierry on June 28, 2017, 11:24 p.m.

Details

Message ID 20170628232427.28425-1-michel.thierry@intel.com
State New
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Series "drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle" ( rev: 1 ) in Intel GFX

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Commit Message

Michel Thierry June 28, 2017, 11:24 p.m.
There's no need to keep reading random registers in i915_swizzle_info if
the platform is not doing GPU side swizzling.

After HSW, swizzling is not used, and the CPU's memory controller
performs all the address swizzling modifications, commit be292e1563ac5b
("drm/i915/bdw: Let the memory controller do all the swizzling").

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 5 +++++
 1 file changed, 5 insertions(+)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 87e13131f6ea..e82f503389fb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2152,6 +2152,11 @@  static int i915_swizzle_info(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 
+	if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
+		seq_puts(m, "not supported - CPU does all the swizzling\n");
+		return 0;
+	}
+
 	intel_runtime_pm_get(dev_priv);
 
 	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",

Comments

On Wed, Jun 28, 2017 at 04:24:27PM -0700, Michel Thierry wrote:
> There's no need to keep reading random registers in i915_swizzle_info if
> the platform is not doing GPU side swizzling.
> 
> After HSW, swizzling is not used, and the CPU's memory controller
> performs all the address swizzling modifications, commit be292e1563ac5b
> ("drm/i915/bdw: Let the memory controller do all the swizzling").

But BDW still contains the registers and hardware capability no? So
might be a good idea to be able to check that it's not misconfigured.

> 
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 87e13131f6ea..e82f503389fb 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2152,6 +2152,11 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>  
> +	if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
> +		seq_puts(m, "not supported - CPU does all the swizzling\n");
> +		return 0;
> +	}
> +
>  	intel_runtime_pm_get(dev_priv);
>  
>  	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
> -- 
> 2.11.0
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Ville Syrjälä (2017-06-29 14:05:25)
> On Wed, Jun 28, 2017 at 04:24:27PM -0700, Michel Thierry wrote:
> > There's no need to keep reading random registers in i915_swizzle_info if
> > the platform is not doing GPU side swizzling.
> > 
> > After HSW, swizzling is not used, and the CPU's memory controller
> > performs all the address swizzling modifications, commit be292e1563ac5b
> > ("drm/i915/bdw: Let the memory controller do all the swizzling").
> 
> But BDW still contains the registers and hardware capability no? So
> might be a good idea to be able to check that it's not misconfigured.

Especially in debugfs where it is useful to show both the hw state and
what we thought it should be.
-Chris
On 6/29/2017 6:07 AM, Chris Wilson wrote:
> Quoting Ville Syrjälä (2017-06-29 14:05:25)
>> On Wed, Jun 28, 2017 at 04:24:27PM -0700, Michel Thierry wrote:
>>> There's no need to keep reading random registers in i915_swizzle_info if
>>> the platform is not doing GPU side swizzling.
>>>
>>> After HSW, swizzling is not used, and the CPU's memory controller
>>> performs all the address swizzling modifications, commit be292e1563ac5b
>>> ("drm/i915/bdw: Let the memory controller do all the swizzling").
>>
>> But BDW still contains the registers and hardware capability no? So
>> might be a good idea to be able to check that it's not misconfigured.
> 
> Especially in debugfs where it is useful to show both the hw state and
> what we thought it should be.

Hi,

Yes, the registers are still there (but this may change). Are you ok if 
I change this to apply only to GEN9+?