[V2] backend: refine the local copy propagation.

Submitted by rander on June 15, 2017, 1:47 a.m.

Details

Message ID 1497491255-30682-1-git-send-email-rander.wang@intel.com
State New
Headers show
Series "backend: refine the local copy propagation." ( rev: 2 ) in Beignet

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Commit Message

rander June 15, 2017, 1:47 a.m.
src modifier is not supported by some instructions.
	so return false when it exists. This fix piglit %
	scalar-arithmetic-int failed

	V2: (1)add hadd rhadd
	    (2)confirmed math functions support midifer except IDIV/Mod

Signed-off-by: rander.wang <rander.wang@intel.com>
---
 .../src/backend/gen_insn_selection_optimize.cpp    | 34 ++++++++++++++++++++++
 1 file changed, 34 insertions(+)

Patch hide | download patch | download mbox

diff --git a/backend/src/backend/gen_insn_selection_optimize.cpp b/backend/src/backend/gen_insn_selection_optimize.cpp
index 07547ec..c35ee25 100644
--- a/backend/src/backend/gen_insn_selection_optimize.cpp
+++ b/backend/src/backend/gen_insn_selection_optimize.cpp
@@ -189,6 +189,40 @@  namespace gbe
     if (insn.opcode == SEL_OP_BSWAP) //should remove once bswap issue is fixed
       return false;
 
+    //the src modifier is not supported by the following instructions
+    if(info->replacement.negation || info->replacement.absolute)
+    {
+      switch(insn.opcode)
+      {
+        case SEL_OP_MATH:
+        {
+          switch(insn.extra.function)
+          {
+            case GEN_MATH_FUNCTION_INT_DIV_QUOTIENT:
+            case GEN_MATH_FUNCTION_INT_DIV_REMAINDER:
+            case GEN_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
+              return false;
+            default:
+              break;
+          }
+
+          break;
+        }
+        case SEL_OP_CBIT:
+        case SEL_OP_FBH:
+        case SEL_OP_FBL:
+        case SEL_OP_BRC:
+        case SEL_OP_BRD:
+        case SEL_OP_BFREV:
+        case SEL_OP_LZD:
+        case SEL_OP_HADD:
+        case SEL_OP_RHADD
+          return false;
+        default:
+          break;
+      }
+    }
+
     if (insn.isWrite() || insn.isRead()) //register in selection vector
       return false;
 

Comments

Fix a build error "case SEL_OP_RHADD" by manual, pushed, thanks.


> -----Original Message-----

> From: Beignet [mailto:beignet-bounces@lists.freedesktop.org] On Behalf Of

> rander.wang

> Sent: Thursday, June 15, 2017 9:48

> To: beignet@freedesktop.org

> Cc: Wang, Rander <rander.wang@intel.com>

> Subject: [Beignet] [PATCH V2] backend: refine the local copy propagation.

> 

> 	src modifier is not supported by some instructions.

> 	so return false when it exists. This fix piglit %

> 	scalar-arithmetic-int failed

> 

> 	V2: (1)add hadd rhadd

> 	    (2)confirmed math functions support midifer except IDIV/Mod

> 

> Signed-off-by: rander.wang <rander.wang@intel.com>

> ---

>  .../src/backend/gen_insn_selection_optimize.cpp    | 34

> ++++++++++++++++++++++

>  1 file changed, 34 insertions(+)

> 

> diff --git a/backend/src/backend/gen_insn_selection_optimize.cpp

> b/backend/src/backend/gen_insn_selection_optimize.cpp

> index 07547ec..c35ee25 100644

> --- a/backend/src/backend/gen_insn_selection_optimize.cpp

> +++ b/backend/src/backend/gen_insn_selection_optimize.cpp

> @@ -189,6 +189,40 @@ namespace gbe

>      if (insn.opcode == SEL_OP_BSWAP) //should remove once bswap issue is

> fixed

>        return false;

> 

> +    //the src modifier is not supported by the following instructions

> +    if(info->replacement.negation || info->replacement.absolute)

> +    {

> +      switch(insn.opcode)

> +      {

> +        case SEL_OP_MATH:

> +        {

> +          switch(insn.extra.function)

> +          {

> +            case GEN_MATH_FUNCTION_INT_DIV_QUOTIENT:

> +            case GEN_MATH_FUNCTION_INT_DIV_REMAINDER:

> +            case

> GEN_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:

> +              return false;

> +            default:

> +              break;

> +          }

> +

> +          break;

> +        }

> +        case SEL_OP_CBIT:

> +        case SEL_OP_FBH:

> +        case SEL_OP_FBL:

> +        case SEL_OP_BRC:

> +        case SEL_OP_BRD:

> +        case SEL_OP_BFREV:

> +        case SEL_OP_LZD:

> +        case SEL_OP_HADD:

> +        case SEL_OP_RHADD

> +          return false;

> +        default:

> +          break;

> +      }

> +    }

> +

>      if (insn.isWrite() || insn.isRead()) //register in selection vector

>        return false;

> 

> --

> 2.7.4

> 

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