[02/18] drm/amdgpu: abstract gart aperture initialization for gfxhub/mmhub

Submitted by Huang, Ray on May 31, 2017, 4:14 p.m.

Details

Message ID 1496247293-16429-3-git-send-email-ray.huang@amd.com
State New
Headers show
Series "Vega10 S3 following up" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Huang, Ray May 31, 2017, 4:14 p.m.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 34 +++++++++++++++++---------------
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 33 +++++++++++++++++--------------
 2 files changed, 36 insertions(+), 31 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 8cf30b7..b21607c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -49,6 +49,23 @@  static void gfxhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
 		(u32)(value >> 32));
 }
 
+static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
+{
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
+		(u32)(adev->mc.gtt_start >> 12));
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
+		(u32)(adev->mc.gtt_start >> 44));
+
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
+		(u32)(adev->mc.gtt_end >> 12));
+	WREG32(SOC15_REG_OFFSET(GC, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
+		(u32)(adev->mc.gtt_end >> 44));
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -57,8 +74,8 @@  int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 
 	/* Program MC. */
 	gfxhub_v1_0_init_pt_regs(adev);
+	gfxhub_v1_0_init_gart_aperture_regs(adev);
 
-	/* Update configuration */
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),
 		adev->mc.vram_start >> 18);
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),
@@ -159,21 +176,6 @@  int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 			    0);
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);
 
-	/* setup context0 */
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
-		(u32)(adev->mc.gtt_start >> 12));
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
-		(u32)(adev->mc.gtt_start >> 44));
-
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
-		(u32)(adev->mc.gtt_end >> 12));
-	WREG32(SOC15_REG_OFFSET(GC, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
-		(u32)(adev->mc.gtt_end >> 44));
-
 	WREG32(SOC15_REG_OFFSET(GC, 0,
 				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
 		(u32)(adev->dummy_page.addr >> 12));
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 84eb3a3..84cdca2 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -62,6 +62,23 @@  static void mmhub_v1_0_init_pt_regs(struct amdgpu_device *adev)
 		(u32)(value >> 32));
 }
 
+static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
+{
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
+		(u32)(adev->mc.gtt_start >> 12));
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
+		(u32)(adev->mc.gtt_start >> 44));
+
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
+		(u32)(adev->mc.gtt_end >> 12));
+	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
+				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
+		(u32)(adev->mc.gtt_end >> 44));
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
 	u32 tmp;
@@ -71,6 +88,7 @@  int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 
 	/* Program MC. */
 	mmhub_v1_0_init_pt_regs(adev);
+	mmhub_v1_0_init_gart_aperture_regs(adev);
 
 	/* Update configuration */
 	DRM_INFO("%s -- in\n", __func__);
@@ -173,21 +191,6 @@  int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 			    0);
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);
 
-	/* setup context0 */
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),
-		(u32)(adev->mc.gtt_start >> 12));
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),
-		(u32)(adev->mc.gtt_start >> 44));
-
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),
-		(u32)(adev->mc.gtt_end >> 12));
-	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
-				mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),
-		(u32)(adev->mc.gtt_end >> 44));
-
 	WREG32(SOC15_REG_OFFSET(MMHUB, 0,
 				mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),
 		(u32)(adev->dummy_page.addr >> 12));

Comments

> -----Original Message-----

> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf

> Of Huang Rui

> Sent: Wednesday, May 31, 2017 12:15 PM

> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander; Koenig, Christian

> Cc: Wang, Ken; Huang, Ray; Huan, Alvin

> Subject: [PATCH 02/18] drm/amdgpu: abstract gart aperture initialization for

> gfxhub/mmhub

> 

> Signed-off-by: Huang Rui <ray.huang@amd.com>

> ---

>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 34 +++++++++++++++++--

> -------------

>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 33 +++++++++++++++++-

> -------------

>  2 files changed, 36 insertions(+), 31 deletions(-)

> 

> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

> index 8cf30b7..b21607c 100644

> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

> @@ -49,6 +49,23 @@ static void gfxhub_v1_0_init_pt_regs(struct

> amdgpu_device *adev)

>  		(u32)(value >> 32));

>  }

> 

> +static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device

> *adev)


I think we can merge code from patch 1 into this function as well rather than having two functions since the page table base is technically part of the gart aperture.  Same for mmhub.

Alex

> +{

> +	WREG32(SOC15_REG_OFFSET(GC, 0,

> +

> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),

> +		(u32)(adev->mc.gtt_start >> 12));

> +	WREG32(SOC15_REG_OFFSET(GC, 0,

> +

> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),

> +		(u32)(adev->mc.gtt_start >> 44));

> +

> +	WREG32(SOC15_REG_OFFSET(GC, 0,

> +

> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),

> +		(u32)(adev->mc.gtt_end >> 12));

> +	WREG32(SOC15_REG_OFFSET(GC, 0,

> +

> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),

> +		(u32)(adev->mc.gtt_end >> 44));

> +}

> +

>  int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)

>  {

>  	u32 tmp;

> @@ -57,8 +74,8 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device

> *adev)

> 

>  	/* Program MC. */

>  	gfxhub_v1_0_init_pt_regs(adev);

> +	gfxhub_v1_0_init_gart_aperture_regs(adev);

> 

> -	/* Update configuration */

>  	WREG32(SOC15_REG_OFFSET(GC, 0,

> mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),

>  		adev->mc.vram_start >> 18);

>  	WREG32(SOC15_REG_OFFSET(GC, 0,

> mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),

> @@ -159,21 +176,6 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device

> *adev)

>  			    0);

>  	WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp);

> 

> -	/* setup context0 */

> -	WREG32(SOC15_REG_OFFSET(GC, 0,

> -

> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),

> -		(u32)(adev->mc.gtt_start >> 12));

> -	WREG32(SOC15_REG_OFFSET(GC, 0,

> -

> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),

> -		(u32)(adev->mc.gtt_start >> 44));

> -

> -	WREG32(SOC15_REG_OFFSET(GC, 0,

> -

> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),

> -		(u32)(adev->mc.gtt_end >> 12));

> -	WREG32(SOC15_REG_OFFSET(GC, 0,

> -

> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),

> -		(u32)(adev->mc.gtt_end >> 44));

> -

>  	WREG32(SOC15_REG_OFFSET(GC, 0,

> 

> 	mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),

>  		(u32)(adev->dummy_page.addr >> 12));

> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

> index 84eb3a3..84cdca2 100644

> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

> @@ -62,6 +62,23 @@ static void mmhub_v1_0_init_pt_regs(struct

> amdgpu_device *adev)

>  		(u32)(value >> 32));

>  }

> 

> +static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device

> *adev)

> +{

> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

> +

> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),

> +		(u32)(adev->mc.gtt_start >> 12));

> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

> +

> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),

> +		(u32)(adev->mc.gtt_start >> 44));

> +

> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

> +

> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),

> +		(u32)(adev->mc.gtt_end >> 12));

> +	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

> +

> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),

> +		(u32)(adev->mc.gtt_end >> 44));

> +}

> +

>  int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)

>  {

>  	u32 tmp;

> @@ -71,6 +88,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device

> *adev)

> 

>  	/* Program MC. */

>  	mmhub_v1_0_init_pt_regs(adev);

> +	mmhub_v1_0_init_gart_aperture_regs(adev);

> 

>  	/* Update configuration */

>  	DRM_INFO("%s -- in\n", __func__);

> @@ -173,21 +191,6 @@ int mmhub_v1_0_gart_enable(struct

> amdgpu_device *adev)

>  			    0);

>  	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_CNTL4), tmp);

> 

> -	/* setup context0 */

> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

> -

> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),

> -		(u32)(adev->mc.gtt_start >> 12));

> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

> -

> 	mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),

> -		(u32)(adev->mc.gtt_start >> 44));

> -

> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

> -

> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),

> -		(u32)(adev->mc.gtt_end >> 12));

> -	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

> -

> 	mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),

> -		(u32)(adev->mc.gtt_end >> 44));

> -

>  	WREG32(SOC15_REG_OFFSET(MMHUB, 0,

> 

> 	mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),

>  		(u32)(adev->dummy_page.addr >> 12));

> --

> 2.7.4

> 

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