[11/11] drm/amdgpu/uvd7: add UVD hw init sequences for sriov

Submitted by Yu, Xiangliang on April 24, 2017, 6:58 a.m.

Details

Message ID 1493017089-23101-12-git-send-email-Xiangliang.Yu@amd.com
State New
Headers show
Series "Enable UVD and PSP loading for SRIOV" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Yu, Xiangliang April 24, 2017, 6:58 a.m.
From: Frank Min <Frank.Min@amd.com>

Add UVD hw init.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 92 ++++++++++++++++++++---------------
 1 file changed, 54 insertions(+), 38 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index a294f05..e0b7ded 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -368,7 +368,10 @@  static int uvd_v7_0_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	adev->uvd.num_enc_rings = 2;
+	if (amdgpu_sriov_vf(adev))
+		adev->uvd.num_enc_rings = 1;
+	else
+		adev->uvd.num_enc_rings = 2;
 	uvd_v7_0_set_ring_funcs(adev);
 	uvd_v7_0_set_enc_ring_funcs(adev);
 	uvd_v7_0_set_irq_funcs(adev);
@@ -421,12 +424,14 @@  static int uvd_v7_0_sw_init(void *handle)
 	r = amdgpu_uvd_resume(adev);
 	if (r)
 		return r;
+	if (!amdgpu_sriov_vf(adev)) {
+		ring = &adev->uvd.ring;
+		sprintf(ring->name, "uvd");
+		r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+		if (r)
+			return r;
+	}
 
-	ring = &adev->uvd.ring;
-	sprintf(ring->name, "uvd");
-	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
-	if (r)
-		return r;
 
 	for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 		ring = &adev->uvd.ring_enc[i];
@@ -445,6 +450,10 @@  static int uvd_v7_0_sw_init(void *handle)
 			return r;
 	}
 
+	r = amdgpu_virt_alloc_mm_table(adev);
+	if (r)
+		return r;
+
 	return r;
 }
 
@@ -453,6 +462,8 @@  static int uvd_v7_0_sw_fini(void *handle)
 	int i, r;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+	amdgpu_virt_free_mm_table(adev);
+
 	r = amdgpu_uvd_suspend(adev);
 	if (r)
 		return r;
@@ -479,48 +490,53 @@  static int uvd_v7_0_hw_init(void *handle)
 	uint32_t tmp;
 	int i, r;
 
-	r = uvd_v7_0_start(adev);
+	if (amdgpu_sriov_vf(adev))
+		r = uvd_v7_0_sriov_start(adev);
+	else
+		r = uvd_v7_0_start(adev);
 	if (r)
 		goto done;
 
-	ring->ready = true;
-	r = amdgpu_ring_test_ring(ring);
-	if (r) {
-		ring->ready = false;
-		goto done;
-	}
+	if (!amdgpu_sriov_vf(adev)) {
+		ring->ready = true;
+		r = amdgpu_ring_test_ring(ring);
+		if (r) {
+			ring->ready = false;
+			goto done;
+		}
 
-	r = amdgpu_ring_alloc(ring, 10);
-	if (r) {
-		DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
-		goto done;
-	}
+		r = amdgpu_ring_alloc(ring, 10);
+		if (r) {
+			DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
+			goto done;
+		}
 
-	tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
-		mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
-	amdgpu_ring_write(ring, tmp);
-	amdgpu_ring_write(ring, 0xFFFFF);
+		tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
+			mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
+		amdgpu_ring_write(ring, tmp);
+		amdgpu_ring_write(ring, 0xFFFFF);
 
-	tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
-		mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
-	amdgpu_ring_write(ring, tmp);
-	amdgpu_ring_write(ring, 0xFFFFF);
+		tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
+			mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
+		amdgpu_ring_write(ring, tmp);
+		amdgpu_ring_write(ring, 0xFFFFF);
 
-	tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
-		mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
-	amdgpu_ring_write(ring, tmp);
-	amdgpu_ring_write(ring, 0xFFFFF);
+		tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
+			mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
+		amdgpu_ring_write(ring, tmp);
+		amdgpu_ring_write(ring, 0xFFFFF);
 
-	/* Clear timeout status bits */
-	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
-		mmUVD_SEMA_TIMEOUT_STATUS), 0));
-	amdgpu_ring_write(ring, 0x8);
+		/* Clear timeout status bits */
+		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
+			mmUVD_SEMA_TIMEOUT_STATUS), 0));
+		amdgpu_ring_write(ring, 0x8);
 
-	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
-		mmUVD_SEMA_CNTL), 0));
-	amdgpu_ring_write(ring, 3);
+		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
+			mmUVD_SEMA_CNTL), 0));
+		amdgpu_ring_write(ring, 3);
 
-	amdgpu_ring_commit(ring);
+		amdgpu_ring_commit(ring);
+	}
 
 	for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 		ring = &adev->uvd.ring_enc[i];

Comments

> -----Original Message-----

> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf

> Of Xiangliang Yu

> Sent: Monday, April 24, 2017 2:58 AM

> To: amd-gfx@lists.freedesktop.org

> Cc: Yu, Xiangliang; Min, Frank

> Subject: [PATCH 11/11] drm/amdgpu/uvd7: add UVD hw init sequences for

> sriov

> 

> From: Frank Min <Frank.Min@amd.com>

> 

> Add UVD hw init.

> 

> Signed-off-by: Frank Min <Frank.Min@amd.com>

> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>


This needs to land before patch 6 as well.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>


> ---

>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 92 ++++++++++++++++++++--

> -------------

>  1 file changed, 54 insertions(+), 38 deletions(-)

> 

> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

> index a294f05..e0b7ded 100644

> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

> @@ -368,7 +368,10 @@ static int uvd_v7_0_early_init(void *handle)

>  {

>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

> 

> -	adev->uvd.num_enc_rings = 2;

> +	if (amdgpu_sriov_vf(adev))

> +		adev->uvd.num_enc_rings = 1;

> +	else

> +		adev->uvd.num_enc_rings = 2;

>  	uvd_v7_0_set_ring_funcs(adev);

>  	uvd_v7_0_set_enc_ring_funcs(adev);

>  	uvd_v7_0_set_irq_funcs(adev);

> @@ -421,12 +424,14 @@ static int uvd_v7_0_sw_init(void *handle)

>  	r = amdgpu_uvd_resume(adev);

>  	if (r)

>  		return r;

> +	if (!amdgpu_sriov_vf(adev)) {

> +		ring = &adev->uvd.ring;

> +		sprintf(ring->name, "uvd");

> +		r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);

> +		if (r)

> +			return r;

> +	}

> 

> -	ring = &adev->uvd.ring;

> -	sprintf(ring->name, "uvd");

> -	r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);

> -	if (r)

> -		return r;

> 

>  	for (i = 0; i < adev->uvd.num_enc_rings; ++i) {

>  		ring = &adev->uvd.ring_enc[i];

> @@ -445,6 +450,10 @@ static int uvd_v7_0_sw_init(void *handle)

>  			return r;

>  	}

> 

> +	r = amdgpu_virt_alloc_mm_table(adev);

> +	if (r)

> +		return r;

> +

>  	return r;

>  }

> 

> @@ -453,6 +462,8 @@ static int uvd_v7_0_sw_fini(void *handle)

>  	int i, r;

>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

> 

> +	amdgpu_virt_free_mm_table(adev);

> +

>  	r = amdgpu_uvd_suspend(adev);

>  	if (r)

>  		return r;

> @@ -479,48 +490,53 @@ static int uvd_v7_0_hw_init(void *handle)

>  	uint32_t tmp;

>  	int i, r;

> 

> -	r = uvd_v7_0_start(adev);

> +	if (amdgpu_sriov_vf(adev))

> +		r = uvd_v7_0_sriov_start(adev);

> +	else

> +		r = uvd_v7_0_start(adev);

>  	if (r)

>  		goto done;

> 

> -	ring->ready = true;

> -	r = amdgpu_ring_test_ring(ring);

> -	if (r) {

> -		ring->ready = false;

> -		goto done;

> -	}

> +	if (!amdgpu_sriov_vf(adev)) {

> +		ring->ready = true;

> +		r = amdgpu_ring_test_ring(ring);

> +		if (r) {

> +			ring->ready = false;

> +			goto done;

> +		}

> 

> -	r = amdgpu_ring_alloc(ring, 10);

> -	if (r) {

> -		DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n",

> r);

> -		goto done;

> -	}

> +		r = amdgpu_ring_alloc(ring, 10);

> +		if (r) {

> +			DRM_ERROR("amdgpu: ring failed to lock UVD ring

> (%d).\n", r);

> +			goto done;

> +		}

> 

> -	tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,

> -		mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);

> -	amdgpu_ring_write(ring, tmp);

> -	amdgpu_ring_write(ring, 0xFFFFF);

> +		tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,

> +			mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);

> +		amdgpu_ring_write(ring, tmp);

> +		amdgpu_ring_write(ring, 0xFFFFF);

> 

> -	tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,

> -		mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);

> -	amdgpu_ring_write(ring, tmp);

> -	amdgpu_ring_write(ring, 0xFFFFF);

> +		tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,

> +

> 	mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);

> +		amdgpu_ring_write(ring, tmp);

> +		amdgpu_ring_write(ring, 0xFFFFF);

> 

> -	tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,

> -		mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);

> -	amdgpu_ring_write(ring, tmp);

> -	amdgpu_ring_write(ring, 0xFFFFF);

> +		tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,

> +

> 	mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);

> +		amdgpu_ring_write(ring, tmp);

> +		amdgpu_ring_write(ring, 0xFFFFF);

> 

> -	/* Clear timeout status bits */

> -	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,

> -		mmUVD_SEMA_TIMEOUT_STATUS), 0));

> -	amdgpu_ring_write(ring, 0x8);

> +		/* Clear timeout status bits */

> +		amdgpu_ring_write(ring,

> PACKET0(SOC15_REG_OFFSET(UVD, 0,

> +			mmUVD_SEMA_TIMEOUT_STATUS), 0));

> +		amdgpu_ring_write(ring, 0x8);

> 

> -	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,

> -		mmUVD_SEMA_CNTL), 0));

> -	amdgpu_ring_write(ring, 3);

> +		amdgpu_ring_write(ring,

> PACKET0(SOC15_REG_OFFSET(UVD, 0,

> +			mmUVD_SEMA_CNTL), 0));

> +		amdgpu_ring_write(ring, 3);

> 

> -	amdgpu_ring_commit(ring);

> +		amdgpu_ring_commit(ring);

> +	}

> 

>  	for (i = 0; i < adev->uvd.num_enc_rings; ++i) {

>  		ring = &adev->uvd.ring_enc[i];

> --

> 2.7.4

> 

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