[05/11] drm/amdgpu/vce4: move mm table constructions functions into mmsch header file

Submitted by Yu, Xiangliang on April 24, 2017, 6:58 a.m.

Details

Message ID 1493017089-23101-6-git-send-email-Xiangliang.Yu@amd.com
State New
Headers show
Series "Enable UVD and PSP loading for SRIOV" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Yu, Xiangliang April 24, 2017, 6:58 a.m.
From: Frank Min <Frank.Min@amd.com>

Move mm table construction functions into mmsch header file so that
UVD can reuse it.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h | 57 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c   | 57 ---------------------------------
 2 files changed, 57 insertions(+), 57 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h b/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
index 5f0fc8b..f048f91 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
@@ -84,4 +84,61 @@  struct mmsch_v1_0_cmd_indirect_write {
 	uint32_t reg_value;
 };
 
+static inline void mmsch_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write *direct_wt,
+					  uint32_t *init_table,
+					  uint32_t reg_offset,
+					  uint32_t value)
+{
+	direct_wt->cmd_header.reg_offset = reg_offset;
+	direct_wt->reg_value = value;
+	memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v1_0_cmd_direct_write));
+}
+
+static inline void mmsch_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt,
+						 uint32_t *init_table,
+						 uint32_t reg_offset,
+						 uint32_t mask, uint32_t data)
+{
+	direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
+	direct_rd_mod_wt->mask_value = mask;
+	direct_rd_mod_wt->write_data = data;
+	memcpy((void *)init_table, direct_rd_mod_wt,
+	       sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write));
+}
+
+static inline void mmsch_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling *direct_poll,
+					    uint32_t *init_table,
+					    uint32_t reg_offset,
+					    uint32_t mask, uint32_t wait)
+{
+	direct_poll->cmd_header.reg_offset = reg_offset;
+	direct_poll->mask_value = mask;
+	direct_poll->wait_value = wait;
+	memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v1_0_cmd_direct_polling));
+}
+
+#define INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
+	mmsch_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \
+				      init_table, (reg), \
+				      (mask), (data)); \
+	init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \
+	table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \
+}
+
+#define INSERT_DIRECT_WT(reg, value) { \
+	mmsch_insert_direct_wt(&direct_wt, \
+			       init_table, (reg), \
+			       (value)); \
+	init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
+	table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
+}
+
+#define INSERT_DIRECT_POLL(reg, mask, wait) { \
+	mmsch_insert_direct_poll(&direct_poll, \
+				 init_table, (reg), \
+				 (mask), (wait)); \
+	init_table += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
+	table_size += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
+}
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 1deb546..a3d9d4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -49,63 +49,6 @@  static void vce_v4_0_mc_resume(struct amdgpu_device *adev);
 static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev);
 static void vce_v4_0_set_irq_funcs(struct amdgpu_device *adev);
 
-static inline void mmsch_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write *direct_wt,
-					  uint32_t *init_table,
-					  uint32_t reg_offset,
-					  uint32_t value)
-{
-	direct_wt->cmd_header.reg_offset = reg_offset;
-	direct_wt->reg_value = value;
-	memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v1_0_cmd_direct_write));
-}
-
-static inline void mmsch_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt,
-						 uint32_t *init_table,
-						 uint32_t reg_offset,
-						 uint32_t mask, uint32_t data)
-{
-	direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
-	direct_rd_mod_wt->mask_value = mask;
-	direct_rd_mod_wt->write_data = data;
-	memcpy((void *)init_table, direct_rd_mod_wt,
-	       sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write));
-}
-
-static inline void mmsch_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling *direct_poll,
-					    uint32_t *init_table,
-					    uint32_t reg_offset,
-					    uint32_t mask, uint32_t wait)
-{
-	direct_poll->cmd_header.reg_offset = reg_offset;
-	direct_poll->mask_value = mask;
-	direct_poll->wait_value = wait;
-	memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v1_0_cmd_direct_polling));
-}
-
-#define INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
-	mmsch_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \
-				      init_table, (reg), \
-				      (mask), (data)); \
-	init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \
-	table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \
-}
-
-#define INSERT_DIRECT_WT(reg, value) { \
-	mmsch_insert_direct_wt(&direct_wt, \
-			       init_table, (reg), \
-			       (value)); \
-	init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
-	table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
-}
-
-#define INSERT_DIRECT_POLL(reg, mask, wait) { \
-	mmsch_insert_direct_poll(&direct_poll, \
-				 init_table, (reg), \
-				 (mask), (wait)); \
-	init_table += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
-	table_size += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
-}
-
 /**
  * vce_v4_0_ring_get_rptr - get read pointer
  *

Comments

> -----Original Message-----

> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf

> Of Xiangliang Yu

> Sent: Monday, April 24, 2017 2:58 AM

> To: amd-gfx@lists.freedesktop.org

> Cc: Yu, Xiangliang; Min, Frank

> Subject: [PATCH 05/11] drm/amdgpu/vce4: move mm table constructions

> functions into mmsch header file

> 

> From: Frank Min <Frank.Min@amd.com>

> 

> Move mm table construction functions into mmsch header file so that

> UVD can reuse it.

> 

> Signed-off-by: Frank Min <Frank.Min@amd.com>

> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>

> ---

>  drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h | 57

> +++++++++++++++++++++++++++++++++

>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c   | 57 ---------------------------------

>  2 files changed, 57 insertions(+), 57 deletions(-)

> 

> diff --git a/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

> b/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

> index 5f0fc8b..f048f91 100644

> --- a/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

> +++ b/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

> @@ -84,4 +84,61 @@ struct mmsch_v1_0_cmd_indirect_write {

>  	uint32_t reg_value;

>  };

> 

> +static inline void mmsch_insert_direct_wt(struct


Please change the names of the exported functions to have the v1_0 in the name.  E.g.,
mmsch_v1_0_insert_direct_wt()
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>


> mmsch_v1_0_cmd_direct_write *direct_wt,

> +					  uint32_t *init_table,

> +					  uint32_t reg_offset,

> +					  uint32_t value)

> +{

> +	direct_wt->cmd_header.reg_offset = reg_offset;

> +	direct_wt->reg_value = value;

> +	memcpy((void *)init_table, direct_wt, sizeof(struct

> mmsch_v1_0_cmd_direct_write));

> +}

> +

> +static inline void mmsch_insert_direct_rd_mod_wt(struct

> mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt,

> +						 uint32_t *init_table,

> +						 uint32_t reg_offset,

> +						 uint32_t mask, uint32_t data)

> +{

> +	direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;

> +	direct_rd_mod_wt->mask_value = mask;

> +	direct_rd_mod_wt->write_data = data;

> +	memcpy((void *)init_table, direct_rd_mod_wt,

> +	       sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write));

> +}

> +

> +static inline void mmsch_insert_direct_poll(struct

> mmsch_v1_0_cmd_direct_polling *direct_poll,

> +					    uint32_t *init_table,

> +					    uint32_t reg_offset,

> +					    uint32_t mask, uint32_t wait)

> +{

> +	direct_poll->cmd_header.reg_offset = reg_offset;

> +	direct_poll->mask_value = mask;

> +	direct_poll->wait_value = wait;

> +	memcpy((void *)init_table, direct_poll, sizeof(struct

> mmsch_v1_0_cmd_direct_polling));

> +}

> +

> +#define INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \

> +	mmsch_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \

> +				      init_table, (reg), \

> +				      (mask), (data)); \

> +	init_table += sizeof(struct

> mmsch_v1_0_cmd_direct_read_modify_write)/4; \

> +	table_size += sizeof(struct

> mmsch_v1_0_cmd_direct_read_modify_write)/4; \

> +}

> +

> +#define INSERT_DIRECT_WT(reg, value) { \

> +	mmsch_insert_direct_wt(&direct_wt, \

> +			       init_table, (reg), \

> +			       (value)); \

> +	init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \

> +	table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \

> +}

> +

> +#define INSERT_DIRECT_POLL(reg, mask, wait) { \

> +	mmsch_insert_direct_poll(&direct_poll, \

> +				 init_table, (reg), \

> +				 (mask), (wait)); \

> +	init_table += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \

> +	table_size += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \

> +}

> +

>  #endif

> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

> index 1deb546..a3d9d4d 100644

> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

> @@ -49,63 +49,6 @@ static void vce_v4_0_mc_resume(struct

> amdgpu_device *adev);

>  static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev);

>  static void vce_v4_0_set_irq_funcs(struct amdgpu_device *adev);

> 

> -static inline void mmsch_insert_direct_wt(struct

> mmsch_v1_0_cmd_direct_write *direct_wt,

> -					  uint32_t *init_table,

> -					  uint32_t reg_offset,

> -					  uint32_t value)

> -{

> -	direct_wt->cmd_header.reg_offset = reg_offset;

> -	direct_wt->reg_value = value;

> -	memcpy((void *)init_table, direct_wt, sizeof(struct

> mmsch_v1_0_cmd_direct_write));

> -}

> -

> -static inline void mmsch_insert_direct_rd_mod_wt(struct

> mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt,

> -						 uint32_t *init_table,

> -						 uint32_t reg_offset,

> -						 uint32_t mask, uint32_t data)

> -{

> -	direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;

> -	direct_rd_mod_wt->mask_value = mask;

> -	direct_rd_mod_wt->write_data = data;

> -	memcpy((void *)init_table, direct_rd_mod_wt,

> -	       sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write));

> -}

> -

> -static inline void mmsch_insert_direct_poll(struct

> mmsch_v1_0_cmd_direct_polling *direct_poll,

> -					    uint32_t *init_table,

> -					    uint32_t reg_offset,

> -					    uint32_t mask, uint32_t wait)

> -{

> -	direct_poll->cmd_header.reg_offset = reg_offset;

> -	direct_poll->mask_value = mask;

> -	direct_poll->wait_value = wait;

> -	memcpy((void *)init_table, direct_poll, sizeof(struct

> mmsch_v1_0_cmd_direct_polling));

> -}

> -

> -#define INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \

> -	mmsch_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \

> -				      init_table, (reg), \

> -				      (mask), (data)); \

> -	init_table += sizeof(struct

> mmsch_v1_0_cmd_direct_read_modify_write)/4; \

> -	table_size += sizeof(struct

> mmsch_v1_0_cmd_direct_read_modify_write)/4; \

> -}

> -

> -#define INSERT_DIRECT_WT(reg, value) { \

> -	mmsch_insert_direct_wt(&direct_wt, \

> -			       init_table, (reg), \

> -			       (value)); \

> -	init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \

> -	table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \

> -}

> -

> -#define INSERT_DIRECT_POLL(reg, mask, wait) { \

> -	mmsch_insert_direct_poll(&direct_poll, \

> -				 init_table, (reg), \

> -				 (mask), (wait)); \

> -	init_table += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \

> -	table_size += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \

> -}

> -

>  /**

>   * vce_v4_0_ring_get_rptr - get read pointer

>   *

> --

> 2.7.4

> 

> _______________________________________________

> amd-gfx mailing list

> amd-gfx@lists.freedesktop.org

> https://lists.freedesktop.org/mailman/listinfo/amd-gfx