[04/11] drm/amdgpu/vce4: fix a PSP loading VCE issue

Submitted by Yu, Xiangliang on April 24, 2017, 6:58 a.m.

Details

Message ID 1493017089-23101-5-git-send-email-Xiangliang.Yu@amd.com
State New
Headers show
Series "Enable UVD and PSP loading for SRIOV" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Yu, Xiangliang April 24, 2017, 6:58 a.m.
From: Daniel Wang <Daniel.Wang2@amd.com>

Fixed PSP loading issue for sriov.

Signed-off-by: Daniel Wang <Daniel.Wang2@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 76fc8ed..1deb546 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -291,9 +291,21 @@  static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
 		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);
 		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);
 
-		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), adev->vce.gpu_addr >> 8);
-		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), adev->vce.gpu_addr >> 8);
-		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), adev->vce.gpu_addr >> 8);
+		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
+				adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
+		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
+				adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
+		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
+				adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);
+		} else {
+		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),
+				adev->vce.gpu_addr >> 8);
+		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),
+				adev->vce.gpu_addr >> 8);
+		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),
+				adev->vce.gpu_addr >> 8);
+		}
 
 		offset = AMDGPU_VCE_FIRMWARE_OFFSET;
 		size = VCE_V4_0_FW_SIZE;

Comments

> -----Original Message-----

> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf

> Of Xiangliang Yu

> Sent: Monday, April 24, 2017 2:58 AM

> To: amd-gfx@lists.freedesktop.org

> Cc: Wang, Daniel(Xiaowei); Yu, Xiangliang

> Subject: [PATCH 04/11] drm/amdgpu/vce4: fix a PSP loading VCE issue

> 

> From: Daniel Wang <Daniel.Wang2@amd.com>

> 

> Fixed PSP loading issue for sriov.

> 

> Signed-off-by: Daniel Wang <Daniel.Wang2@amd.com>

> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>


Acked-by: Alex Deucher <alexander.deucher@amd.com>


> ---

>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 18 +++++++++++++++---

>  1 file changed, 15 insertions(+), 3 deletions(-)

> 

> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

> index 76fc8ed..1deb546 100644

> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

> @@ -291,9 +291,21 @@ static int vce_v4_0_sriov_start(struct

> amdgpu_device *adev)

>  		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

> mmVCE_LMI_SWAP_CNTL1), 0);

>  		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

> mmVCE_LMI_VM_CTRL), 0);

> 

> -		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

> mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), adev->vce.gpu_addr >> 8);

> -		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

> mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), adev->vce.gpu_addr >> 8);

> -		INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

> mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), adev->vce.gpu_addr >> 8);

> +		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)

> {

> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

> mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),

> +				adev-

> >firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);

> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

> mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),

> +				adev-

> >firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);

> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

> mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),

> +				adev-

> >firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8);

> +		} else {

> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

> mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),

> +				adev->vce.gpu_addr >> 8);

> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

> mmVCE_LMI_VCPU_CACHE_40BIT_BAR1),

> +				adev->vce.gpu_addr >> 8);

> +		    INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0,

> mmVCE_LMI_VCPU_CACHE_40BIT_BAR2),

> +				adev->vce.gpu_addr >> 8);

> +		}

> 

>  		offset = AMDGPU_VCE_FIRMWARE_OFFSET;

>  		size = VCE_V4_0_FW_SIZE;

> --

> 2.7.4

> 

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