[libdrm,4/7] tests/amdgpu: fix the count number for vega10

Submitted by Marek Olšák on March 21, 2017, 7:56 p.m.

Details

Message ID 1490126185-4482-5-git-send-email-maraeo@gmail.com
State New
Headers show
Series "Vega10 bits for libdrm and more" ( rev: 1 ) in AMD X.Org drivers

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Commit Message

Marek Olšák March 21, 2017, 7:56 p.m.
From: Huang Rui <ray.huang@amd.com>

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
---
 tests/amdgpu/basic_tests.c | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

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diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index bfda21b..4dce67e 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -796,26 +796,30 @@  static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle,
 static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
 {
 	const int sdma_write_length = 128;
 	const int pm4_dw = 256;
 	amdgpu_context_handle context_handle;
 	amdgpu_bo_handle bo;
 	amdgpu_bo_handle *resources;
 	uint32_t *pm4;
 	struct amdgpu_cs_ib_info *ib_info;
 	struct amdgpu_cs_request *ibs_request;
+	struct amdgpu_gpu_info gpu_info = {0};
 	uint64_t bo_mc;
 	volatile uint32_t *bo_cpu;
 	int i, j, r, loop;
 	uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
 	amdgpu_va_handle va_handle;
 
+	r = amdgpu_query_gpu_info(device_handle, &gpu_info);
+	CU_ASSERT_EQUAL(r, 0);
+
 	pm4 = calloc(pm4_dw, sizeof(*pm4));
 	CU_ASSERT_NOT_EQUAL(pm4, NULL);
 
 	ib_info = calloc(1, sizeof(*ib_info));
 	CU_ASSERT_NOT_EQUAL(ib_info, NULL);
 
 	ibs_request = calloc(1, sizeof(*ibs_request));
 	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
 
 	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
@@ -841,21 +845,24 @@  static void amdgpu_command_submission_write_linear_helper(unsigned ip_type)
 
 		resources[0] = bo;
 
 		/* fulfill PM4: test DMA write-linear */
 		i = j = 0;
 		if (ip_type == AMDGPU_HW_IP_DMA) {
 			pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
 					       SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
 			pm4[i++] = 0xffffffff & bo_mc;
 			pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
-			pm4[i++] = sdma_write_length;
+			if (gpu_info.family_id >= AMDGPU_FAMILY_AI)
+				pm4[i++] = sdma_write_length - 1;
+			else
+				pm4[i++] = sdma_write_length;
 			while(j++ < sdma_write_length)
 				pm4[i++] = 0xdeadbeaf;
 		} else if ((ip_type == AMDGPU_HW_IP_GFX) ||
 			   (ip_type == AMDGPU_HW_IP_COMPUTE)) {
 			pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length);
 			pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 			pm4[i++] = 0xfffffffc & bo_mc;
 			pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
 			while(j++ < sdma_write_length)
 				pm4[i++] = 0xdeadbeaf;
@@ -897,26 +904,30 @@  static void amdgpu_command_submission_sdma_write_linear(void)
 static void amdgpu_command_submission_const_fill_helper(unsigned ip_type)
 {
 	const int sdma_write_length = 1024 * 1024;
 	const int pm4_dw = 256;
 	amdgpu_context_handle context_handle;
 	amdgpu_bo_handle bo;
 	amdgpu_bo_handle *resources;
 	uint32_t *pm4;
 	struct amdgpu_cs_ib_info *ib_info;
 	struct amdgpu_cs_request *ibs_request;
+	struct amdgpu_gpu_info gpu_info = {0};
 	uint64_t bo_mc;
 	volatile uint32_t *bo_cpu;
 	int i, j, r, loop;
 	uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
 	amdgpu_va_handle va_handle;
 
+	r = amdgpu_query_gpu_info(device_handle, &gpu_info);
+	CU_ASSERT_EQUAL(r, 0);
+
 	pm4 = calloc(pm4_dw, sizeof(*pm4));
 	CU_ASSERT_NOT_EQUAL(pm4, NULL);
 
 	ib_info = calloc(1, sizeof(*ib_info));
 	CU_ASSERT_NOT_EQUAL(ib_info, NULL);
 
 	ibs_request = calloc(1, sizeof(*ibs_request));
 	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
 
 	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
@@ -942,21 +953,24 @@  static void amdgpu_command_submission_const_fill_helper(unsigned ip_type)
 		resources[0] = bo;
 
 		/* fulfill PM4: test DMA const fill */
 		i = j = 0;
 		if (ip_type == AMDGPU_HW_IP_DMA) {
 			pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0,
 					       SDMA_CONSTANT_FILL_EXTRA_SIZE(2));
 			pm4[i++] = 0xffffffff & bo_mc;
 			pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32;
 			pm4[i++] = 0xdeadbeaf;
-			pm4[i++] = sdma_write_length;
+			if (gpu_info.family_id >= AMDGPU_FAMILY_AI)
+				pm4[i++] = sdma_write_length - 1;
+			else
+				pm4[i++] = sdma_write_length;
 		} else if ((ip_type == AMDGPU_HW_IP_GFX) ||
 			   (ip_type == AMDGPU_HW_IP_COMPUTE)) {
 			pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5);
 			pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) |
 				PACKET3_DMA_DATA_DST_SEL(0) |
 				PACKET3_DMA_DATA_SRC_SEL(2) |
 				PACKET3_DMA_DATA_CP_SYNC;
 			pm4[i++] = 0xdeadbeaf;
 			pm4[i++] = 0;
 			pm4[i++] = 0xfffffffc & bo_mc;
@@ -1000,26 +1014,30 @@  static void amdgpu_command_submission_sdma_const_fill(void)
 static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type)
 {
 	const int sdma_write_length = 1024;
 	const int pm4_dw = 256;
 	amdgpu_context_handle context_handle;
 	amdgpu_bo_handle bo1, bo2;
 	amdgpu_bo_handle *resources;
 	uint32_t *pm4;
 	struct amdgpu_cs_ib_info *ib_info;
 	struct amdgpu_cs_request *ibs_request;
+	struct amdgpu_gpu_info gpu_info = {0};
 	uint64_t bo1_mc, bo2_mc;
 	volatile unsigned char *bo1_cpu, *bo2_cpu;
 	int i, j, r, loop1, loop2;
 	uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
 	amdgpu_va_handle bo1_va_handle, bo2_va_handle;
 
+	r = amdgpu_query_gpu_info(device_handle, &gpu_info);
+	CU_ASSERT_EQUAL(r, 0);
+
 	pm4 = calloc(pm4_dw, sizeof(*pm4));
 	CU_ASSERT_NOT_EQUAL(pm4, NULL);
 
 	ib_info = calloc(1, sizeof(*ib_info));
 	CU_ASSERT_NOT_EQUAL(ib_info, NULL);
 
 	ibs_request = calloc(1, sizeof(*ibs_request));
 	CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
 
 	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
@@ -1057,21 +1075,24 @@  static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type)
 			/* clear bo2 */
 			memset((void*)bo2_cpu, 0, sdma_write_length);
 
 			resources[0] = bo1;
 			resources[1] = bo2;
 
 			/* fulfill PM4: test DMA copy linear */
 			i = j = 0;
 			if (ip_type == AMDGPU_HW_IP_DMA) {
 				pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
-				pm4[i++] = sdma_write_length;
+				if (gpu_info.family_id >= AMDGPU_FAMILY_AI)
+					pm4[i++] = sdma_write_length - 1;
+				else
+					pm4[i++] = sdma_write_length;
 				pm4[i++] = 0;
 				pm4[i++] = 0xffffffff & bo1_mc;
 				pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
 				pm4[i++] = 0xffffffff & bo2_mc;
 				pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
 			} else if ((ip_type == AMDGPU_HW_IP_GFX) ||
 				   (ip_type == AMDGPU_HW_IP_COMPUTE)) {
 				pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5);
 				pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) |
 					PACKET3_DMA_DATA_DST_SEL(0) |