[v5,8/18] secboot: disable falcon interrupts when running blob

Submitted by Alexandre Courbot on Dec. 14, 2016, 8:02 a.m.

Details

Message ID cdf21af1f2ebaf9d1ea3ecdb9b53ff42a91f55bc.1481702469.git-series.acourbot@nvidia.com
State New
Headers show
Series "Secure Boot refactoring" ( rev: 1 ) in Nouveau

Not browsing as part of any series.

Commit Message

Alexandre Courbot Dec. 14, 2016, 8:02 a.m.
Make sure we are not disturbed by spurious interrupts, as we poll the
halt bit anyway.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
 drm/nouveau/nvkm/subdev/secboot/gm200.c | 7 +++++++
 1 file changed, 7 insertions(+), 0 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drm/nouveau/nvkm/subdev/secboot/gm200.c
index f6a11e2a8434..2fcb2f761a54 100644
--- a/drm/nouveau/nvkm/subdev/secboot/gm200.c
+++ b/drm/nouveau/nvkm/subdev/secboot/gm200.c
@@ -27,6 +27,7 @@ 
 #include <core/gpuobj.h>
 #include <subdev/fb.h>
 #include <engine/falcon.h>
+#include <subdev/mc.h>
 
 /**
  * gm200_secboot_run_blob() - run the given high-secure blob
@@ -63,6 +64,9 @@  gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob)
 	if (ret)
 		goto end;
 
+	/* Disable interrupts as we will poll for the HALT bit */
+	nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, false);
+
 	/* Start the HS bootloader */
 	nvkm_falcon_set_start_addr(falcon, sb->acr->start_address);
 	nvkm_falcon_start(falcon);
@@ -79,6 +83,9 @@  gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob)
 	}
 
 end:
+	/* Reenable interrupts */
+	nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, true);
+
 	/* We don't need the ACR firmware anymore */
 	nvkm_gpuobj_unmap(&vma);
 	nvkm_falcon_put(falcon, subdev);