drm/amdgpu: refine pg code for gfx_v8.

Submitted by StDenis, Tom on Dec. 1, 2016, 1:24 p.m.

Details

Message ID BN6PR12MB176436BACAD823BEA856AE02F78F0@BN6PR12MB1764.namprd12.prod.outlook.com
State New
Headers show
Series "drm/amdgpu: refine pg code for gfx_v8." ( rev: 2 ) in AMD X.Org drivers

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Commit Message

StDenis, Tom Dec. 1, 2016, 1:24 p.m.
Hi Rex,


Given how often we diagnose problems by disabling PG/CG I'd have to offer my NAK to this patch since it prevents me from disabling PG via the command line.


Any reason you want to make it permanently enabled?


Tom

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index c02ae07..fee8c2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3948,8 +3948,10 @@  static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
         temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
         data = mmRLC_SRM_INDEX_CNTL_DATA_0;
         for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
-               amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
-               amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
+               if (unique_indices[i] != 0) {
+                       amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
+                       amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
+               }
         }
         kfree(register_list_format);

@@ -3965,20 +3967,16 @@  static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
 {
         uint32_t data;

-       if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
-                             AMD_PG_SUPPORT_GFX_SMG |
-                             AMD_PG_SUPPORT_GFX_DMG)) {
-               WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
+       WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);

-               data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
-               data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
-               data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
-               data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
-               WREG32(mmRLC_PG_DELAY, data);
+       data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
+       data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
+       data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
+       data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
+       WREG32(mmRLC_PG_DELAY, data);

-               WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
-               WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
-       }
+       WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
+       WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
 }

 static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
@@ -3995,41 +3993,35 @@  static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,

 static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
 {
-       WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 1 : 0);
+       WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
 }

 static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
 {
-       if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
-                             AMD_PG_SUPPORT_GFX_SMG |
-                             AMD_PG_SUPPORT_GFX_DMG |
-                             AMD_PG_SUPPORT_CP |
-                             AMD_PG_SUPPORT_GDS |
-                             AMD_PG_SUPPORT_RLC_SMU_HS)) {
-               gfx_v8_0_init_csb(adev);
-               gfx_v8_0_init_save_restore_list(adev);
-               gfx_v8_0_enable_save_restore_machine(adev);
-
-               if ((adev->asic_type == CHIP_CARRIZO) ||
-                   (adev->asic_type == CHIP_STONEY)) {
-                       WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
-                       gfx_v8_0_init_power_gating(adev);
-                       WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
-                       if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
-                               cz_enable_sck_slow_down_on_power_up(adev, true);
-                               cz_enable_sck_slow_down_on_power_down(adev, true);
-                       } else {
-                               cz_enable_sck_slow_down_on_power_up(adev, false);
-                               cz_enable_sck_slow_down_on_power_down(adev, false);
-                       }
-                       if (adev->pg_flags & AMD_PG_SUPPORT_CP)
-                               cz_enable_cp_power_gating(adev, true);
-                       else
-                               cz_enable_cp_power_gating(adev, false);
-               } else if (adev->asic_type == CHIP_POLARIS11) {
-                       gfx_v8_0_init_power_gating(adev);
+       gfx_v8_0_init_csb(adev);
+       gfx_v8_0_init_save_restore_list(adev);
+       gfx_v8_0_enable_save_restore_machine(adev);
+
+       if ((adev->asic_type == CHIP_CARRIZO) ||
+           (adev->asic_type == CHIP_STONEY)) {
+               WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
+               gfx_v8_0_init_power_gating(adev);
+               WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
+               if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
+                       cz_enable_sck_slow_down_on_power_up(adev, true);
+                       cz_enable_sck_slow_down_on_power_down(adev, true);
+               } else {
+                       cz_enable_sck_slow_down_on_power_up(adev, false);
+                       cz_enable_sck_slow_down_on_power_down(adev, false);
                 }
+               if (adev->pg_flags & AMD_PG_SUPPORT_CP)
+                       cz_enable_cp_power_gating(adev, true);
+               else
+                       cz_enable_cp_power_gating(adev, false);
+       } else if (adev->asic_type == CHIP_POLARIS11) {
+               gfx_v8_0_init_power_gating(adev);
         }
+
 }

 static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
@@ -5570,14 +5562,11 @@  static int gfx_v8_0_set_powergating_state(void *handle,
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;

-       if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
-               return 0;
-
         switch (adev->asic_type) {
         case CHIP_CARRIZO:
         case CHIP_STONEY:
-               if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
-                       cz_update_gfx_cg_power_gating(adev, enable);
+
+               cz_update_gfx_cg_power_gating(adev, enable);

                 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
                         gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);