[5/7] drm/amd/dal: program HDMI_DATA_SCRAMBLER bit for HDMI 2.0

Submitted by Harry Wentland on Nov. 30, 2016, 7:20 p.m.

Details

Message ID 20161130192013.11043-6-harry.wentland@amd.com
State New
Headers show
Series "dal patches for nov 30, 2016" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Harry Wentland Nov. 30, 2016, 7:20 p.m.
Change-Id: Iad39ffaf361001fc84572a3f902c827c9d4ee1d8
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 .../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c    | 39 ++++++++++++++++++----
 .../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h    |  4 +++
 2 files changed, 37 insertions(+), 6 deletions(-)

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diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
index c573a87fbff3..842182ce93a8 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
@@ -59,11 +59,6 @@  DP_COMPONENT_DEPTH_RESERVED              = 0x00000005,
 #define DP_BLANK_MAX_RETRY 20
 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
 
-#ifndef HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK
-	#define HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x2
-	#define HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1
-#endif
-
 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
 	#define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK       0x00000010L
 	#define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK         0x00000300L
@@ -347,11 +342,19 @@  static void dce110_stream_encoder_hdmi_set_stream_attribute(
 
 	dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
 
-	if (enc110->regs->DIG_FE_CNTL) {
+	/* setup HDMI engine */
+	if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
 		REG_UPDATE_3(HDMI_CONTROL,
 			HDMI_PACKET_GEN_VERSION, 1,
 			HDMI_KEEPOUT_MODE, 1,
 			HDMI_DEEP_COLOR_ENABLE, 0);
+	} else if (enc110->regs->DIG_FE_CNTL) {
+		REG_UPDATE_5(HDMI_CONTROL,
+			HDMI_PACKET_GEN_VERSION, 1,
+			HDMI_KEEPOUT_MODE, 1,
+			HDMI_DEEP_COLOR_ENABLE, 0,
+			HDMI_DATA_SCRAMBLE_EN, 0,
+			HDMI_CLOCK_CHANNEL_RATE, 0);
 	}
 
 	switch (crtc_timing->display_color_depth) {
@@ -377,6 +380,30 @@  static void dce110_stream_encoder_hdmi_set_stream_attribute(
 		break;
 	}
 
+	if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
+		if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
+			/* enable HDMI data scrambler
+			 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
+			 * Clock channel frequency is 1/4 of character rate.
+			 */
+			REG_UPDATE_2(HDMI_CONTROL,
+				HDMI_DATA_SCRAMBLE_EN, 1,
+				HDMI_CLOCK_CHANNEL_RATE, 1);
+		} else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
+
+			/* TODO: New feature for DCE11, still need to implement */
+
+			/* enable HDMI data scrambler
+			 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
+			 * Clock channel frequency is the same
+			 * as character rate
+			 */
+			REG_UPDATE_2(HDMI_CONTROL,
+				HDMI_DATA_SCRAMBLE_EN, 1,
+				HDMI_CLOCK_CHANNEL_RATE, 0);
+		}
+	}
+
 	REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
 		HDMI_GC_CONT, 1,
 		HDMI_GC_SEND, 1,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
index c34b52a186b6..458a37000956 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
@@ -196,6 +196,7 @@ 
 	SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
 	SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
 	SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
+	SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
 	SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
 	SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh)
 
@@ -203,6 +204,7 @@ 
 	SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\
 	SE_SF(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
 	SE_SF(HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
+	SE_SF(HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
 	SE_SF(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
 	SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
 	SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
@@ -252,6 +254,7 @@  struct dce_stream_encoder_shift {
 	uint8_t HDMI_GC_CONT;
 	uint8_t HDMI_GC_SEND;
 	uint8_t HDMI_NULL_SEND;
+	uint8_t HDMI_DATA_SCRAMBLE_EN;
 	uint8_t HDMI_AUDIO_INFO_SEND;
 	uint8_t AFMT_AUDIO_INFO_UPDATE;
 	uint8_t HDMI_AUDIO_INFO_LINE;
@@ -379,6 +382,7 @@  struct dce_stream_encoder_mask {
 	uint32_t HDMI_GC_CONT;
 	uint32_t HDMI_GC_SEND;
 	uint32_t HDMI_NULL_SEND;
+	uint32_t HDMI_DATA_SCRAMBLE_EN;
 	uint32_t HDMI_AUDIO_INFO_SEND;
 	uint32_t AFMT_AUDIO_INFO_UPDATE;
 	uint32_t HDMI_AUDIO_INFO_LINE;