drm/amdgpu/cik_sdma: clean up rb address calculation

Submitted by Alex Deucher on Nov. 23, 2016, 8:27 p.m.

Details

Message ID 1479932826-3362-3-git-send-email-alexander.deucher@amd.com
State New
Headers show
Series "drm/amdgpu/gfx8: move eop programming per queue" ( rev: 3 ) in AMD X.Org drivers

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Commit Message

Alex Deucher Nov. 23, 2016, 8:27 p.m.
Make it clearer what we are doing.

Reviewed-by: Christian K├Ânig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

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diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 4c34dbc..0f34bd1 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -384,6 +384,7 @@  static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 	u32 rb_cntl, ib_cntl;
 	u32 rb_bufsz;
 	u32 wb_offset;
+	u64 gpu_addr;
 	int i, j, r;
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -430,8 +431,10 @@  static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
 
 		rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
 
-		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
-		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
+		gpu_addr = ring->gpu_addr;
+		gpu_addr >>= 8;
+		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], lower_32_bits(gpu_addr));
+		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], upper_32_bits(gpu_addr));
 
 		ring->wptr = 0;
 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);