[73/76] drm/amd/dal: Add reg check before access.

Submitted by Harry Wentland on Nov. 21, 2016, 11:01 p.m.

Details

Message ID 20161121230136.5208-74-harry.wentland@amd.com
State New
Headers show
Series "DAL Patches Nov 21, 2016" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Harry Wentland Nov. 21, 2016, 11:01 p.m.
From: Yongqiang Sun <yongqiang.sun@amd.com>

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c | 4 ----
 drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h | 8 --------
 2 files changed, 12 deletions(-)

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diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
index 050fef92f545..93ce4967e56b 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
@@ -231,9 +231,6 @@  static void dce110_stream_encoder_dp_set_stream_attribute(
 	uint32_t h_back_porch;
 	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
 
-	/* for bring up, disable dp double  TODO */
-	REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1);
-
 	/* set pixel encoding */
 	switch (crtc_timing->pixel_encoding) {
 	case PIXEL_ENCODING_YCBCR422:
@@ -269,7 +266,6 @@  static void dce110_stream_encoder_dp_set_stream_attribute(
 		break;
 	}
 
-	misc1 = REG_READ(DP_MSA_MISC);
 	/* set color depth */
 
 	switch (crtc_timing->display_color_depth) {
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
index 2778f89e5abf..c34b52a186b6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
@@ -515,14 +515,6 @@  struct dce110_stream_enc_registers {
 	uint32_t HDMI_ACR_48_0;
 	uint32_t HDMI_ACR_48_1;
 	uint32_t TMDS_CNTL;
-	uint32_t DP_DB_CNTL;
-	uint32_t DP_MSA_MISC;
-	uint32_t DP_MSA_COLORIMETRY;
-	uint32_t DP_MSA_TIMING_PARAM1;
-	uint32_t DP_MSA_TIMING_PARAM2;
-	uint32_t DP_MSA_TIMING_PARAM3;
-	uint32_t DP_MSA_TIMING_PARAM4;
-	uint32_t HDMI_DB_CONTROL;
 };
 
 struct dce110_stream_encoder {