[57/76] drm/amd/dal: Add YCBCR420 to stream encoder

Submitted by Harry Wentland on Nov. 21, 2016, 11:01 p.m.

Details

Message ID 20161121230136.5208-58-harry.wentland@amd.com
State New
Headers show
Series "DAL Patches Nov 21, 2016" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Harry Wentland Nov. 21, 2016, 11:01 p.m.
From: Zeyu Fan <Zeyu.Fan@amd.com>

Signed-off-by: Zeyu Fan <Zeyu.Fan@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 .../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c    | 37 +++++++++++++++++-----
 .../gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h    |  4 +++
 .../gpu/drm/amd/dal/dc/dce112/dce112_resource.c    |  4 +--
 3 files changed, 35 insertions(+), 10 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
index 98925f9278db..89e09150234e 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.c
@@ -27,11 +27,29 @@ 
 #include "dm_services.h"
 #include "dc_bios_types.h"
 #include "dce_stream_encoder.h"
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-#include "dce/dce_11_0_enum.h"
 #include "reg_helper.h"
 
+enum DP_PIXEL_ENCODING {
+DP_PIXEL_ENCODING_RGB444                 = 0x00000000,
+DP_PIXEL_ENCODING_YCBCR422               = 0x00000001,
+DP_PIXEL_ENCODING_YCBCR444               = 0x00000002,
+DP_PIXEL_ENCODING_RGB_WIDE_GAMUT         = 0x00000003,
+DP_PIXEL_ENCODING_Y_ONLY                 = 0x00000004,
+DP_PIXEL_ENCODING_YCBCR420               = 0x00000005,
+DP_PIXEL_ENCODING_RESERVED               = 0x00000006,
+};
+
+
+enum DP_COMPONENT_DEPTH {
+DP_COMPONENT_DEPTH_6BPC                  = 0x00000000,
+DP_COMPONENT_DEPTH_8BPC                  = 0x00000001,
+DP_COMPONENT_DEPTH_10BPC                 = 0x00000002,
+DP_COMPONENT_DEPTH_12BPC                 = 0x00000003,
+DP_COMPONENT_DEPTH_16BPC                 = 0x00000004,
+DP_COMPONENT_DEPTH_RESERVED              = 0x00000005,
+};
+
+
 #define REG(reg)\
 	(enc110->regs->reg)
 
@@ -221,14 +239,12 @@  static void dce110_stream_encoder_dp_set_stream_attribute(
 	/* set pixel encoding */
 	switch (crtc_timing->pixel_encoding) {
 	case PIXEL_ENCODING_YCBCR422:
-
 		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 				DP_PIXEL_ENCODING_YCBCR422);
-
 		break;
 	case PIXEL_ENCODING_YCBCR444:
 		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
-				PIXEL_ENCODING_YCBCR444);
+				DP_PIXEL_ENCODING_YCBCR444);
 
 		if (crtc_timing->flags.Y_ONLY)
 			if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
@@ -237,13 +253,18 @@  static void dce110_stream_encoder_dp_set_stream_attribute(
 				 * 8, 10, 12, 16 bits */
 				REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 						DP_PIXEL_ENCODING_Y_ONLY);
-
-
 		/* Note: DP_MSA_MISC1 bit 7 is the indicator
 		 * of Y-only mode.
 		 * This bit is set in HW if register
 		 * DP_PIXEL_ENCODING is programmed to 0x4 */
 		break;
+	case PIXEL_ENCODING_YCBCR420:
+		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
+				DP_PIXEL_ENCODING_YCBCR420);
+		if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
+			REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
+
+		break;
 	default:
 		REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
 				DP_PIXEL_ENCODING_RGB444);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
index 88ef2a1f2a43..2778f89e5abf 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_stream_encoder.h
@@ -330,6 +330,8 @@  struct dce_stream_encoder_shift {
 	uint8_t DP_MSA_HWIDTH;
 	uint8_t DP_MSA_VHEIGHT;
 	uint8_t HDMI_DB_DISABLE;
+	uint8_t DP_VID_N_MUL;
+	uint8_t DP_VID_M_DOUBLE_VALUE_EN;
 };
 
 struct dce_stream_encoder_mask {
@@ -455,6 +457,8 @@  struct dce_stream_encoder_mask {
 	uint32_t DP_MSA_HWIDTH;
 	uint32_t DP_MSA_VHEIGHT;
 	uint32_t HDMI_DB_DISABLE;
+	uint32_t DP_VID_N_MUL;
+	uint32_t DP_VID_M_DOUBLE_VALUE_EN;
 };
 
 struct dce110_stream_enc_registers {
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 578d8fd89d39..9f47bec557ea 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -298,11 +298,11 @@  static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 };
 
 static const struct dce_stream_encoder_shift se_shift = {
-		SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
+		SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
 };
 
 static const struct dce_stream_encoder_mask se_mask = {
-		SE_COMMON_MASK_SH_LIST_DCE110(_MASK)
+		SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
 };
 
 #define audio_regs(id)\