[72/76] drm/amd/dal: consolidate mem_input

Submitted by Harry Wentland on Nov. 21, 2016, 11:01 p.m.

Details

Message ID 20161121230136.5208-73-harry.wentland@amd.com
State New
Headers show
Series "DAL Patches Nov 21, 2016" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Harry Wentland Nov. 21, 2016, 11:01 p.m.
From: Tony Cheng <tony.cheng@amd.com>

- create dce_mem_input with regsiter offset/shift/mask abstracted
- move program_surface_config to new method

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/dal/dc/dce/Makefile            |   3 +-
 drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c     | 193 ++++++++++++++
 drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h     | 134 ++++++++++
 .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    |  29 ++-
 .../gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c   | 278 +--------------------
 .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    |  25 +-
 .../gpu/drm/amd/dal/dc/dce112/dce112_resource.c    |  29 ++-
 drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c |   2 +-
 drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c  |  29 ++-
 drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h      |   6 +
 drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |   2 +
 11 files changed, 439 insertions(+), 291 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c
 create mode 100644 drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/dal/dc/dce/Makefile b/drivers/gpu/drm/amd/dal/dc/dce/Makefile
index 738f33f64d64..be757b84790a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/Makefile
+++ b/drivers/gpu/drm/amd/dal/dc/dce/Makefile
@@ -5,7 +5,8 @@ 
 #   - register programming through common macros that look up register 
 #     offset/shift/mask stored in dce_hw struct
 
-DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o
+DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \
+dce_mem_input.o
 
 AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
 
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c
new file mode 100644
index 000000000000..1b4a5b9bb8b6
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.c
@@ -0,0 +1,193 @@ 
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "mem_input.h"
+#include "reg_helper.h"
+
+#define CTX \
+	mi->ctx
+#define REG(reg)\
+	mi->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+	mi->shifts->field_name, mi->masks->field_name
+
+
+
+static void program_tiling(struct mem_input *mi,
+	const union dc_tiling_info *info)
+{
+	if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */
+		REG_UPDATE_9(GRPH_CONTROL,
+				GRPH_NUM_BANKS, info->gfx8.num_banks,
+				GRPH_BANK_WIDTH, info->gfx8.bank_width,
+				GRPH_BANK_HEIGHT, info->gfx8.bank_height,
+				GRPH_MACRO_TILE_ASPECT, info->gfx8.tile_aspect,
+				GRPH_TILE_SPLIT, info->gfx8.tile_split,
+				GRPH_MICRO_TILE_MODE, info->gfx8.tile_mode,
+				GRPH_PIPE_CONFIG, info->gfx8.pipe_config,
+				GRPH_ARRAY_MODE, info->gfx8.array_mode,
+				GRPH_COLOR_EXPANSION_MODE, 1);
+		/* 01 - DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP: zero expansion for YCbCr */
+		/*
+				GRPH_Z, 0);
+				*/
+	}
+}
+
+
+static void program_size_and_rotation(
+	struct mem_input *mi,
+	enum dc_rotation_angle rotation,
+	const union plane_size *plane_size)
+{
+	const struct rect *in_rect = &plane_size->grph.surface_size;
+	struct rect hw_rect = plane_size->grph.surface_size;
+	const uint32_t rotation_angles[ROTATION_ANGLE_COUNT] = {
+			[ROTATION_ANGLE_0] = 0,
+			[ROTATION_ANGLE_90] = 1,
+			[ROTATION_ANGLE_180] = 2,
+			[ROTATION_ANGLE_270] = 3,
+	};
+
+	if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) {
+		hw_rect.x = in_rect->y;
+		hw_rect.y = in_rect->x;
+
+		hw_rect.height = in_rect->width;
+		hw_rect.width = in_rect->height;
+	}
+
+	REG_SET(GRPH_X_START, 0,
+			GRPH_X_START, hw_rect.x);
+
+	REG_SET(GRPH_Y_START, 0,
+			GRPH_Y_START, hw_rect.y);
+
+	REG_SET(GRPH_X_END, 0,
+			GRPH_X_END, hw_rect.width);
+
+	REG_SET(GRPH_Y_END, 0,
+			GRPH_Y_END, hw_rect.height);
+
+	REG_SET(GRPH_PITCH, 0,
+			GRPH_PITCH, plane_size->grph.surface_pitch);
+
+	REG_SET(HW_ROTATION, 0,
+			GRPH_ROTATION_ANGLE, rotation_angles[rotation]);
+}
+
+static void program_grph_pixel_format(
+	struct mem_input *mi,
+	enum surface_pixel_format format)
+{
+	uint32_t red_xbar = 0, blue_xbar = 0; /* no swap */
+	uint32_t grph_depth, grph_format;
+	uint32_t sign = 0, floating = 0;
+
+	if (format == SURFACE_PIXEL_FORMAT_GRPH_BGRA8888 ||
+			/*todo: doesn't look like we handle BGRA here,
+			 *  should problem swap endian*/
+		format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 ||
+		format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS ||
+		format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
+		/* ABGR formats */
+		red_xbar = 2;
+		blue_xbar = 2;
+	}
+
+	REG_SET_2(GRPH_SWAP_CNTL, 0,
+			GRPH_RED_CROSSBAR, red_xbar,
+			GRPH_BLUE_CROSSBAR, blue_xbar);
+
+	switch (format) {
+	case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
+		grph_depth = 0;
+		grph_format = 0;
+		break;
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
+		grph_depth = 1;
+		grph_format = 0;
+		break;
+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
+		grph_depth = 1;
+		grph_format = 1;
+		break;
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
+	case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
+		grph_depth = 2;
+		grph_format = 0;
+		break;
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
+		grph_depth = 2;
+		grph_format = 1;
+		break;
+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
+		sign = 1;
+		floating = 1;
+		/* no break */
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: /* shouldn't this get float too? */
+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
+		grph_depth = 3;
+		grph_format = 0;
+		break;
+	default:
+		DC_ERR("unsupported grph pixel format");
+		break;
+	}
+
+	REG_UPDATE_2(GRPH_CONTROL,
+			GRPH_DEPTH, grph_depth,
+			GRPH_FORMAT, grph_format);
+
+	REG_UPDATE_4(PRESCALE_GRPH_CONTROL,
+			GRPH_PRESCALE_SELECT, floating,
+			GRPH_PRESCALE_R_SIGN, sign,
+			GRPH_PRESCALE_G_SIGN, sign,
+			GRPH_PRESCALE_B_SIGN, sign);
+}
+
+bool dce_mem_input_program_surface_config(struct mem_input *mi,
+	enum surface_pixel_format format,
+	union dc_tiling_info *tiling_info,
+	union plane_size *plane_size,
+	enum dc_rotation_angle rotation,
+	struct dc_plane_dcc_param *dcc,
+	bool horizontal_mirror)
+{
+	REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);
+
+	program_tiling(mi, tiling_info);
+	program_size_and_rotation(mi, rotation, plane_size);
+
+	if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
+		format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+		program_grph_pixel_format(mi, format);
+
+	return true;
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h
new file mode 100644
index 000000000000..20b6287efc78
--- /dev/null
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_mem_input.h
@@ -0,0 +1,134 @@ 
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DCE_MEM_INPUT_H__
+#define __DCE_MEM_INPUT_H__
+
+#define MI_REG_LIST(id)\
+	SRI(GRPH_ENABLE, DCP, id),\
+	SRI(GRPH_CONTROL, DCP, id),\
+	SRI(GRPH_X_START, DCP, id),\
+	SRI(GRPH_Y_START, DCP, id),\
+	SRI(GRPH_X_END, DCP, id),\
+	SRI(GRPH_Y_END, DCP, id),\
+	SRI(GRPH_PITCH, DCP, id),\
+	SRI(HW_ROTATION, DCP, id),\
+	SRI(GRPH_SWAP_CNTL, DCP, id),\
+	SRI(PRESCALE_GRPH_CONTROL, DCP, id)
+
+struct dce_mem_input_registers {
+	uint32_t GRPH_ENABLE;
+	uint32_t GRPH_CONTROL;
+	uint32_t GRPH_X_START;
+	uint32_t GRPH_Y_START;
+	uint32_t GRPH_X_END;
+	uint32_t GRPH_Y_END;
+	uint32_t GRPH_PITCH;
+	uint32_t HW_ROTATION;
+	uint32_t GRPH_SWAP_CNTL;
+	uint32_t PRESCALE_GRPH_CONTROL;
+};
+
+/* Set_Filed_for_Block */
+#define SFB(blk_name, reg_name, field_name, post_fix)\
+	.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
+
+#define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
+	SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
+	SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
+	SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\
+	SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\
+	SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\
+	SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\
+	SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh)
+
+#define MI_DCP_MASK_SH_LIST(mask_sh, blk)\
+	SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\
+	SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\
+	SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\
+	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
+	SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\
+	SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\
+	SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\
+	SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\
+	SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\
+	SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\
+	SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\
+	SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\
+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\
+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\
+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\
+	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh)
+
+#define MI_DCE_MASK_SH_LIST(mask_sh)\
+		MI_DCP_MASK_SH_LIST(mask_sh, ),\
+		MI_GFX8_TILE_MASK_SH_LIST(mask_sh, )
+
+#define MI_REG_FIED_LIST(type) \
+	type GRPH_ENABLE; \
+	type GRPH_X_START; \
+	type GRPH_Y_START; \
+	type GRPH_X_END; \
+	type GRPH_Y_END; \
+	type GRPH_PITCH; \
+	type GRPH_ROTATION_ANGLE; \
+	type GRPH_RED_CROSSBAR; \
+	type GRPH_BLUE_CROSSBAR; \
+	type GRPH_PRESCALE_SELECT; \
+	type GRPH_PRESCALE_R_SIGN; \
+	type GRPH_PRESCALE_G_SIGN; \
+	type GRPH_PRESCALE_B_SIGN; \
+	type GRPH_DEPTH; \
+	type GRPH_FORMAT; \
+	type GRPH_NUM_BANKS; \
+	type GRPH_BANK_WIDTH;\
+	type GRPH_BANK_HEIGHT;\
+	type GRPH_MACRO_TILE_ASPECT;\
+	type GRPH_TILE_SPLIT;\
+	type GRPH_MICRO_TILE_MODE;\
+	type GRPH_PIPE_CONFIG;\
+	type GRPH_ARRAY_MODE;\
+	type GRPH_COLOR_EXPANSION_MODE;\
+	type GRPH_SW_MODE; \
+	type GRPH_NUM_SHADER_ENGINES; \
+	type GRPH_NUM_PIPES; \
+
+struct dce_mem_input_shift {
+	MI_REG_FIED_LIST(uint8_t)
+};
+
+struct dce_mem_input_mask {
+	MI_REG_FIED_LIST(uint32_t)
+};
+
+struct mem_input;
+bool dce_mem_input_program_surface_config(struct mem_input *mi,
+	enum surface_pixel_format format,
+	union dc_tiling_info *tiling_info,
+	union plane_size *plane_size,
+	enum dc_rotation_angle rotation,
+	struct dc_plane_dcc_param *dcc,
+	bool horizontal_mirror);
+
+#endif /*__DCE_MEM_INPUT_H__*/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 23791ca55856..c94695e603bd 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -483,6 +483,24 @@  static const struct resource_create_funcs res_create_funcs = {
 	.create_hwseq = dce100_hwseq_create,
 };
 
+#define mi_inst_regs(id) { MI_REG_LIST(id) }
+static const struct dce_mem_input_registers mi_regs[] = {
+		mi_inst_regs(0),
+		mi_inst_regs(1),
+		mi_inst_regs(2),
+		mi_inst_regs(3),
+		mi_inst_regs(4),
+		mi_inst_regs(5),
+};
+
+static const struct dce_mem_input_shift mi_shifts = {
+		MI_DCE_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_mem_input_mask mi_masks = {
+		MI_DCE_MASK_SH_LIST(_MASK)
+};
+
 static struct mem_input *dce100_mem_input_create(
 	struct dc_context *ctx,
 	uint32_t inst,
@@ -494,9 +512,14 @@  static struct mem_input *dce100_mem_input_create(
 	if (!mem_input110)
 		return NULL;
 
-	if (dce110_mem_input_construct(mem_input110,
-				       ctx, inst, offset))
-		return &mem_input110->base;
+	if (dce110_mem_input_construct(mem_input110, ctx, inst, offset)) {
+		struct mem_input *mi = &mem_input110->base;
+
+		mi->regs = &mi_regs[inst];
+		mi->shifts = &mi_shifts;
+		mi->masks = &mi_masks;
+		return mi;
+	}
 
 	BREAK_TO_DEBUGGER();
 	dm_free(mem_input110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
index 834a73222926..4092abe3812d 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_mem_input.c
@@ -90,263 +90,6 @@  static void program_pri_addr(
 				 DCP_REG(mmGRPH_PRIMARY_SURFACE_ADDRESS), value);
 }
 
-static void enable(struct dce110_mem_input *mem_input110)
-{
-	uint32_t value = 0;
-
-	value = dm_read_reg(mem_input110->base.ctx, DCP_REG(mmGRPH_ENABLE));
-	set_reg_field_value(value, 1, GRPH_ENABLE, GRPH_ENABLE);
-	dm_write_reg(mem_input110->base.ctx,
-		DCP_REG(mmGRPH_ENABLE),
-		value);
-}
-
-static void program_tiling(
-	struct dce110_mem_input *mem_input110,
-	const union dc_tiling_info *info,
-	const enum surface_pixel_format pixel_format)
-{
-	uint32_t value = 0;
-
-	value = dm_read_reg(
-			mem_input110->base.ctx,
-			DCP_REG(mmGRPH_CONTROL));
-
-	set_reg_field_value(value, info->gfx8.num_banks,
-		GRPH_CONTROL, GRPH_NUM_BANKS);
-
-	set_reg_field_value(value, info->gfx8.bank_width,
-		GRPH_CONTROL, GRPH_BANK_WIDTH);
-
-	set_reg_field_value(value, info->gfx8.bank_height,
-		GRPH_CONTROL, GRPH_BANK_HEIGHT);
-
-	set_reg_field_value(value, info->gfx8.tile_aspect,
-		GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT);
-
-	set_reg_field_value(value, info->gfx8.tile_split,
-		GRPH_CONTROL, GRPH_TILE_SPLIT);
-
-	set_reg_field_value(value, info->gfx8.tile_mode,
-		GRPH_CONTROL, GRPH_MICRO_TILE_MODE);
-
-	set_reg_field_value(value, info->gfx8.pipe_config,
-		GRPH_CONTROL, GRPH_PIPE_CONFIG);
-
-	set_reg_field_value(value, info->gfx8.array_mode,
-		GRPH_CONTROL, GRPH_ARRAY_MODE);
-
-	set_reg_field_value(value, 1,
-		GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE);
-
-	set_reg_field_value(value, 0,
-		GRPH_CONTROL, GRPH_Z);
-
-	dm_write_reg(
-		mem_input110->base.ctx,
-		DCP_REG(mmGRPH_CONTROL),
-		value);
-}
-
-static void program_size_and_rotation(
-	struct dce110_mem_input *mem_input110,
-	enum dc_rotation_angle rotation,
-	const union plane_size *plane_size)
-{
-	uint32_t value = 0;
-	union plane_size local_size = *plane_size;
-
-	if (rotation == ROTATION_ANGLE_90 ||
-		rotation == ROTATION_ANGLE_270) {
-
-		uint32_t swap;
-
-		swap = local_size.grph.surface_size.x;
-		local_size.grph.surface_size.x =
-			local_size.grph.surface_size.y;
-		local_size.grph.surface_size.y  = swap;
-
-		swap = local_size.grph.surface_size.width;
-		local_size.grph.surface_size.width =
-			local_size.grph.surface_size.height;
-		local_size.grph.surface_size.height = swap;
-	}
-
-	set_reg_field_value(value, local_size.grph.surface_size.x,
-			GRPH_X_START, GRPH_X_START);
-	dm_write_reg(
-		mem_input110->base.ctx,
-		DCP_REG(mmGRPH_X_START),
-		value);
-
-	value = 0;
-	set_reg_field_value(value, local_size.grph.surface_size.y,
-			GRPH_Y_START, GRPH_Y_START);
-	dm_write_reg(
-		mem_input110->base.ctx,
-		DCP_REG(mmGRPH_Y_START),
-		value);
-
-	value = 0;
-	set_reg_field_value(value, local_size.grph.surface_size.width,
-			GRPH_X_END, GRPH_X_END);
-	dm_write_reg(
-		mem_input110->base.ctx,
-		DCP_REG(mmGRPH_X_END),
-		value);
-
-	value = 0;
-	set_reg_field_value(value, local_size.grph.surface_size.height,
-			GRPH_Y_END, GRPH_Y_END);
-	dm_write_reg(
-		mem_input110->base.ctx,
-		DCP_REG(mmGRPH_Y_END),
-		value);
-
-	value = 0;
-	set_reg_field_value(value, local_size.grph.surface_pitch,
-			GRPH_PITCH, GRPH_PITCH);
-	dm_write_reg(
-		mem_input110->base.ctx,
-		DCP_REG(mmGRPH_PITCH),
-		value);
-
-	value = 0;
-	switch (rotation) {
-	case ROTATION_ANGLE_90:
-		set_reg_field_value(value, 1,
-			HW_ROTATION, GRPH_ROTATION_ANGLE);
-		break;
-	case ROTATION_ANGLE_180:
-		set_reg_field_value(value, 2,
-			HW_ROTATION, GRPH_ROTATION_ANGLE);
-		break;
-	case ROTATION_ANGLE_270:
-		set_reg_field_value(value, 3,
-			HW_ROTATION, GRPH_ROTATION_ANGLE);
-		break;
-	default:
-		set_reg_field_value(value, 0,
-			HW_ROTATION, GRPH_ROTATION_ANGLE);
-		break;
-	}
-	dm_write_reg(
-		mem_input110->base.ctx,
-		DCP_REG(mmHW_ROTATION),
-		value);
-}
-
-static void program_pixel_format(
-	struct dce110_mem_input *mem_input110,
-	enum surface_pixel_format format)
-{
-	if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
-		format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
-		uint32_t value = 0;
-
-		/* handle colour twizzle formats, swapping R and B */
-		if (format == SURFACE_PIXEL_FORMAT_GRPH_BGRA8888 ||
-			format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 ||
-			format ==
-			SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS ||
-			format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
-			set_reg_field_value(
-				value, 2, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR);
-			set_reg_field_value(
-				value, 2, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR);
-		}
-
-		dm_write_reg(
-			mem_input110->base.ctx,
-			DCP_REG(mmGRPH_SWAP_CNTL),
-			value);
-
-		value =	dm_read_reg(
-				mem_input110->base.ctx,
-				DCP_REG(mmGRPH_CONTROL));
-
-		switch (format) {
-		case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
-			set_reg_field_value(
-				value, 0, GRPH_CONTROL, GRPH_DEPTH);
-			set_reg_field_value(
-				value, 0, GRPH_CONTROL, GRPH_FORMAT);
-			break;
-		case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
-			set_reg_field_value(
-				value, 1, GRPH_CONTROL, GRPH_DEPTH);
-			set_reg_field_value(
-				value, 1, GRPH_CONTROL, GRPH_FORMAT);
-			break;
-		case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
-		case SURFACE_PIXEL_FORMAT_GRPH_BGRA8888:
-			set_reg_field_value(
-				value, 2, GRPH_CONTROL, GRPH_DEPTH);
-			set_reg_field_value(
-				value, 0, GRPH_CONTROL, GRPH_FORMAT);
-			break;
-		case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
-		case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
-		case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
-			set_reg_field_value(
-				value, 2, GRPH_CONTROL, GRPH_DEPTH);
-			set_reg_field_value(
-				value, 1, GRPH_CONTROL, GRPH_FORMAT);
-			break;
-		case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
-		case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
-		case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
-			set_reg_field_value(
-				value, 3, GRPH_CONTROL, GRPH_DEPTH);
-			set_reg_field_value(
-				value, 0, GRPH_CONTROL, GRPH_FORMAT);
-			break;
-		default:
-			break;
-		}
-		dm_write_reg(
-			mem_input110->base.ctx,
-			DCP_REG(mmGRPH_CONTROL),
-			value);
-
-		value = dm_read_reg(
-			mem_input110->base.ctx,
-			DCP_REG(mmPRESCALE_GRPH_CONTROL));
-
-		if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
-			set_reg_field_value(
-				value, 1, PRESCALE_GRPH_CONTROL,
-				GRPH_PRESCALE_SELECT);
-			set_reg_field_value(
-				value, 1, PRESCALE_GRPH_CONTROL,
-				GRPH_PRESCALE_R_SIGN);
-			set_reg_field_value(
-				value, 1, PRESCALE_GRPH_CONTROL,
-				GRPH_PRESCALE_G_SIGN);
-			set_reg_field_value(
-				value, 1, PRESCALE_GRPH_CONTROL,
-				GRPH_PRESCALE_B_SIGN);
-		} else {
-			set_reg_field_value(
-				value, 0, PRESCALE_GRPH_CONTROL,
-				GRPH_PRESCALE_SELECT);
-			set_reg_field_value(
-				value, 0, PRESCALE_GRPH_CONTROL,
-				GRPH_PRESCALE_R_SIGN);
-			set_reg_field_value(
-				value, 0, PRESCALE_GRPH_CONTROL,
-				GRPH_PRESCALE_G_SIGN);
-			set_reg_field_value(
-				value, 0, PRESCALE_GRPH_CONTROL,
-				GRPH_PRESCALE_B_SIGN);
-		}
-		dm_write_reg(
-			mem_input110->base.ctx,
-			DCP_REG(mmPRESCALE_GRPH_CONTROL),
-			value);
-	}
-}
-
 bool dce110_mem_input_is_flip_pending(struct mem_input *mem_input)
 {
 	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
@@ -518,25 +261,6 @@  bool dce110_mem_input_program_pte_vm(
 	return true;
 }
 
-bool dce110_mem_input_program_surface_config(
-	struct mem_input *mem_input,
-	enum surface_pixel_format format,
-	union dc_tiling_info *tiling_info,
-	union plane_size *plane_size,
-	enum dc_rotation_angle rotation,
-	struct dc_plane_dcc_param *dcc,
-	bool horizotal_mirror)
-{
-	struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);
-
-	enable(mem_input110);
-	program_tiling(mem_input110, tiling_info, format);
-	program_size_and_rotation(mem_input110, rotation, plane_size);
-	program_pixel_format(mem_input110, format);
-
-	return true;
-}
-
 static void program_urgency_watermark(
 	const struct dc_context *ctx,
 	const uint32_t offset,
@@ -981,7 +705,7 @@  static struct mem_input_funcs dce110_mem_input_funcs = {
 	.mem_input_program_pte_vm =
 			dce110_mem_input_program_pte_vm,
 	.mem_input_program_surface_config =
-			dce110_mem_input_program_surface_config,
+			dce_mem_input_program_surface_config,
 	.mem_input_is_flip_pending =
 			dce110_mem_input_is_flip_pending,
 	.mem_input_update_dchub = NULL
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 87ae249779a9..f9cebc9680a6 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -464,6 +464,20 @@  static const struct resource_create_funcs res_create_funcs = {
 	.create_hwseq = dce110_hwseq_create,
 };
 
+#define mi_inst_regs(id) { MI_REG_LIST(id) }
+static const struct dce_mem_input_registers mi_regs[] = {
+		mi_inst_regs(0),
+		mi_inst_regs(1),
+		mi_inst_regs(2),
+};
+
+static const struct dce_mem_input_shift mi_shifts = {
+		MI_DCE_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_mem_input_mask mi_masks = {
+		MI_DCE_MASK_SH_LIST(_MASK)
+};
 
 static struct mem_input *dce110_mem_input_create(
 	struct dc_context *ctx,
@@ -476,9 +490,14 @@  static struct mem_input *dce110_mem_input_create(
 	if (!mem_input110)
 		return NULL;
 
-	if (dce110_mem_input_construct(mem_input110,
-				       ctx, inst, offset))
-		return &mem_input110->base;
+	if (dce110_mem_input_construct(mem_input110, ctx, inst, offset)) {
+		struct mem_input *mi = &mem_input110->base;
+
+		mi->regs = &mi_regs[inst];
+		mi->shifts = &mi_shifts;
+		mi->masks = &mi_masks;
+		return mi;
+	}
 
 	BREAK_TO_DEBUGGER();
 	dm_free(mem_input110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 634541eb55c5..e0b3266fdef0 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -508,6 +508,24 @@  static const struct resource_create_funcs res_create_funcs = {
 	.create_hwseq = dce112_hwseq_create,
 };
 
+#define mi_inst_regs(id) { MI_REG_LIST(id) }
+static const struct dce_mem_input_registers mi_regs[] = {
+		mi_inst_regs(0),
+		mi_inst_regs(1),
+		mi_inst_regs(2),
+		mi_inst_regs(3),
+		mi_inst_regs(4),
+		mi_inst_regs(5),
+};
+
+static const struct dce_mem_input_shift mi_shifts = {
+		MI_DCE_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_mem_input_mask mi_masks = {
+		MI_DCE_MASK_SH_LIST(_MASK)
+};
+
 static struct mem_input *dce112_mem_input_create(
 	struct dc_context *ctx,
 	uint32_t inst,
@@ -519,9 +537,14 @@  static struct mem_input *dce112_mem_input_create(
 	if (!mem_input110)
 		return NULL;
 
-	if (dce112_mem_input_construct(mem_input110,
-				       ctx, inst, offset))
-		return &mem_input110->base;
+	if (dce112_mem_input_construct(mem_input110, ctx, inst, offset)) {
+		struct mem_input *mi = &mem_input110->base;
+
+		mi->regs = &mi_regs[inst];
+		mi->shifts = &mi_shifts;
+		mi->masks = &mi_masks;
+		return mi;
+	}
 
 	BREAK_TO_DEBUGGER();
 	dm_free(mem_input110);
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
index 7cc3ae89b7ee..8da0e31f1b6a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_mem_input.c
@@ -173,7 +173,7 @@  static struct mem_input_funcs dce80_mem_input_funcs = {
 	.mem_input_program_surface_flip_and_addr =
 			dce110_mem_input_program_surface_flip_and_addr,
 	.mem_input_program_surface_config =
-			dce110_mem_input_program_surface_config,
+			dce_mem_input_program_surface_config,
 	.mem_input_is_flip_pending =
 			dce110_mem_input_is_flip_pending,
 	.mem_input_update_dchub = NULL
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 1279136d1764..3de40302eb89 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -474,6 +474,24 @@  static const struct resource_create_funcs res_create_funcs = {
 	.create_hwseq = dce80_hwseq_create,
 };
 
+#define mi_inst_regs(id) { MI_REG_LIST(id) }
+static const struct dce_mem_input_registers mi_regs[] = {
+		mi_inst_regs(0),
+		mi_inst_regs(1),
+		mi_inst_regs(2),
+		mi_inst_regs(3),
+		mi_inst_regs(4),
+		mi_inst_regs(5),
+};
+
+static const struct dce_mem_input_shift mi_shifts = {
+		MI_DCE_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_mem_input_mask mi_masks = {
+		MI_DCE_MASK_SH_LIST(_MASK)
+};
+
 static struct mem_input *dce80_mem_input_create(
 	struct dc_context *ctx,
 	uint32_t inst,
@@ -485,9 +503,14 @@  static struct mem_input *dce80_mem_input_create(
 	if (!mem_input80)
 		return NULL;
 
-	if (dce80_mem_input_construct(mem_input80,
-				      ctx, inst, offsets))
-		return &mem_input80->base;
+	if (dce80_mem_input_construct(mem_input80, ctx, inst, offsets)) {
+		struct mem_input *mi = &mem_input80->base;
+
+		mi->regs = &mi_regs[inst];
+		mi->shifts = &mi_shifts;
+		mi->masks = &mi_masks;
+		return mi;
+	}
 
 	BREAK_TO_DEBUGGER();
 	dm_free(mem_input80);
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
index a4e91cc719d6..e7026ec87bce 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw/mem_input.h
@@ -29,6 +29,8 @@ 
 #include "include/grph_object_id.h"
 #include "inc/bandwidth_calcs.h"
 
+#include "dce/dce_mem_input.h" /* temporary */
+
 struct stutter_modes {
 	bool enhanced;
 	bool quad_dmif_buffer;
@@ -42,6 +44,10 @@  struct mem_input {
 	struct dc_plane_address current_address;
 	uint32_t inst;
 	struct stutter_modes stutter_mode;
+
+	const struct dce_mem_input_registers *regs;
+	const struct dce_mem_input_shift *shifts;
+	const struct dce_mem_input_mask *masks;
 };
 
 struct mem_input_funcs {
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index 16b10dca6e58..d16e70103300 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -44,6 +44,8 @@  enum pipe_lock_control {
 	PIPE_LOCK_CONTROL_MODE = 1 << 4
 };
 
+struct dce_hwseq;
+
 struct hw_sequencer_funcs {
 
 	void (*init_hw)(struct core_dc *dc);