[70/76] drm/amd/dal: dce_crtc_switch_to_clk_src

Submitted by Harry Wentland on Nov. 21, 2016, 11:01 p.m.

Details

Message ID 20161121230136.5208-71-harry.wentland@amd.com
State New
Headers show
Series "DAL Patches Nov 21, 2016" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Harry Wentland Nov. 21, 2016, 11:01 p.m.
From: Tony Cheng <tony.cheng@amd.com>

- fix crtc_switch_to_clk_src
- fix programming phypll ids into ppll

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c         | 36 +++++++++++-
 drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h         | 68 +++++++++++++++++++---
 .../gpu/drm/amd/dal/dc/dce100/dce100_resource.c    |  2 +-
 .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    | 35 +----------
 .../gpu/drm/amd/dal/dc/dce110/dce110_resource.c    | 13 -----
 .../drm/amd/dal/dc/dce112/dce112_hw_sequencer.c    | 35 -----------
 .../gpu/drm/amd/dal/dc/dce112/dce112_resource.c    |  2 +-
 drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h      |  2 -
 8 files changed, 98 insertions(+), 95 deletions(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
index 3a453bf395bb..014043c13d7a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.c
@@ -149,8 +149,7 @@  static void disable_sw_manual_control_light_sleep(void)
 	/* TODO: implement */
 }
 
-void dce_clock_gating_power_up(
-		struct dce_hwseq *hws,
+void dce_clock_gating_power_up(struct dce_hwseq *hws,
 		bool enable)
 {
 	if (enable) {
@@ -161,3 +160,36 @@  void dce_clock_gating_power_up(
 		dce_underlay_clock_enable(hws);
 	}
 }
+
+void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
+		struct clock_source *clk_src,
+		unsigned int tg_inst)
+{
+	if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO) {
+		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
+				DP_DTO0_ENABLE, 1);
+
+	} else if (clk_src->id >= CLOCK_SOURCE_COMBO_PHY_PLL0) {
+		uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0;
+
+		REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
+				PHYPLL_PIXEL_RATE_SOURCE, rate_source,
+				PIXEL_RATE_PLL_SOURCE, 0);
+
+		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
+				DP_DTO0_ENABLE, 0);
+
+	} else if (clk_src->id <= CLOCK_SOURCE_ID_PLL2) {
+		uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;
+
+		REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
+				PIXEL_RATE_SOURCE, rate_source,
+				DP_DTO0_ENABLE, 0);
+
+		if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
+			REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
+					PIXEL_RATE_PLL_SOURCE, 1);
+	} else {
+		DC_ERR("unknown clock source");
+	}
+}
diff --git a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
index 5ec78dcad9b5..4af8d560a7ee 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/dal/dc/dce/dce_hwseq.h
@@ -58,6 +58,22 @@ 
 	SRII(BLND_CONTROL, BLND, 4), \
 	SRII(BLND_CONTROL, BLND, 5)
 
+#define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
+	SRII(PIXEL_RATE_CNTL, blk, 0), \
+	SRII(PIXEL_RATE_CNTL, blk, 1), \
+	SRII(PIXEL_RATE_CNTL, blk, 2), \
+	SRII(PIXEL_RATE_CNTL, blk, 3), \
+	SRII(PIXEL_RATE_CNTL, blk, 4), \
+	SRII(PIXEL_RATE_CNTL, blk, 5)
+
+#define HWSEQ_PHYPLL_REG_LIST(blk) \
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
+
 #define HWSEQ_DCE11_REG_LIST_BASE() \
 	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 	SR(DCFEV_CLOCK_CONTROL), \
@@ -69,11 +85,18 @@ 
 	SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
 	SRII(BLND_CONTROL, BLND, 0),\
 	SRII(BLND_CONTROL, BLND, 1),\
-	SR(BLNDV_CONTROL)
+	SR(BLNDV_CONTROL),\
+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
 
 #define HWSEQ_DCE8_REG_LIST() \
 	HWSEQ_DCEF_REG_LIST_DCE8(), \
-	HWSEQ_BLND_REG_LIST()
+	HWSEQ_BLND_REG_LIST(), \
+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
+
+#define HWSEQ_DCE10_REG_LIST() \
+	HWSEQ_DCEF_REG_LIST(), \
+	HWSEQ_BLND_REG_LIST(), \
+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
 
 #define HWSEQ_ST_REG_LIST() \
 	HWSEQ_DCE11_REG_LIST_BASE(), \
@@ -93,9 +116,10 @@ 
 	.BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \
 	.BLND_CONTROL[3] = mmBLNDV_CONTROL
 
-#define HWSEQ_COMMON_REG_LIST_BASE() \
-	HWSEQ_DCEF_REG_LIST(), \
-	HWSEQ_BLND_REG_LIST()
+#define HWSEQ_DCE112_REG_LIST() \
+	HWSEQ_DCE10_REG_LIST(), \
+	HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
+	HWSEQ_PHYPLL_REG_LIST(CRTC)
 
 struct dce_hwseq_registers {
 	uint32_t DCFE_CLOCK_CONTROL[6];
@@ -104,12 +128,19 @@  struct dce_hwseq_registers {
 	uint32_t BLND_V_UPDATE_LOCK[6];
 	uint32_t BLND_CONTROL[6];
 	uint32_t BLNDV_CONTROL;
+
 	uint32_t CRTC_H_BLANK_START_END[6];
+	uint32_t PIXEL_RATE_CNTL[6];
+	uint32_t PHYPLL_PIXEL_RATE_CNTL[6];
 };
  /* set field name */
 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
 	.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
 
+#define HWS_SF1(blk_name, reg_name, field_name, post_fix)\
+	.field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
+
+
 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\
 	HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\
 	SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
@@ -125,23 +156,35 @@  struct dce_hwseq_registers {
 	HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\
 	HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh)
 
+#define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\
+	HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\
+	HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh)
+
+#define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\
+	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
+	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
+
 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
 	.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
-	HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh)
+	HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
 
 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
 	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
-	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_)
+	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
 
 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
 	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
-	SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh)
+	SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
 
 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
-	HWSEQ_DCE10_MASK_SH_LIST(mask_sh)
+	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
+	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
 
 #define HWSEQ_REG_FIED_LIST(type) \
 	type DCFE_CLOCK_ENABLE; \
@@ -156,6 +199,10 @@  struct dce_hwseq_registers {
 	type BLND_ALPHA_MODE; \
 	type BLND_MODE; \
 	type BLND_MULTIPLIED_MODE; \
+	type DP_DTO0_ENABLE; \
+	type PIXEL_RATE_SOURCE; \
+	type PHYPLL_PIXEL_RATE_SOURCE; \
+	type PIXEL_RATE_PLL_SOURCE; \
 
 struct dce_hwseq_shift {
 	HWSEQ_REG_FIED_LIST(uint8_t)
@@ -197,4 +244,7 @@  void dce_set_blender_mode(struct dce_hwseq *hws,
 void dce_clock_gating_power_up(struct dce_hwseq *hws,
 		bool enable);
 
+void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
+		struct clock_source *clk_src,
+		unsigned int tg_inst);
 #endif   /*__DCE_HWSEQ_H__*/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index 4b8c1e79caaa..23791ca55856 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -451,7 +451,7 @@  static struct stream_encoder *dce100_stream_encoder_create(
 	.reg_name[id] = mm ## block ## id ## _ ## reg_name
 
 static const struct dce_hwseq_registers hwseq_reg = {
-		HWSEQ_COMMON_REG_LIST_BASE()
+		HWSEQ_DCE10_REG_LIST()
 };
 
 static const struct dce_hwseq_shift hwseq_shift = {
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 7ebe090c75f2..ef00588b8179 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -148,35 +148,6 @@  static void dce110_init_pte(struct dc_context *ctx)
 		dm_write_reg(ctx, addr, value);
 	}
 }
-
-static void dce110_crtc_switch_to_clk_src(
-				struct clock_source *clk_src, uint8_t crtc_inst)
-{
-	uint32_t pixel_rate_cntl_value;
-	uint32_t addr;
-
-	/* These addresses are the same across DCE8 - DCE11.2 */
-	addr = mmCRTC0_PIXEL_RATE_CNTL + crtc_inst *
-			(mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL);
-
-	pixel_rate_cntl_value = dm_read_reg(clk_src->ctx, addr);
-
-	if (clk_src->dp_clk_src)
-		set_reg_field_value(pixel_rate_cntl_value, 1,
-			CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE);
-	else {
-		set_reg_field_value(pixel_rate_cntl_value,
-				0,
-				CRTC0_PIXEL_RATE_CNTL,
-				DP_DTO0_ENABLE);
-
-		set_reg_field_value(pixel_rate_cntl_value,
-				clk_src->id - CLOCK_SOURCE_ID_PLL0,
-				CRTC0_PIXEL_RATE_CNTL,
-				CRTC0_PIXEL_RATE_SOURCE);
-	}
-	dm_write_reg(clk_src->ctx, addr, pixel_rate_cntl_value);
-}
 /**************************************************************************/
 
 static void enable_display_pipe_clock_gating(
@@ -1037,7 +1008,8 @@  static void switch_dp_clock_sources(
 					res_ctx, pipe_ctx->clock_source);
 				pipe_ctx->clock_source = clk_src;
 				resource_reference_clock_source(res_ctx, clk_src);
-				dc->hwss.crtc_switch_to_clk_src(clk_src, i);
+
+				dce_crtc_switch_to_clk_src(dc->hwseq, clk_src, i);
 			}
 		}
 	}
@@ -1278,7 +1250,7 @@  enum dc_status dce110_apply_ctx_to_hw(
 
 		if (pipe_ctx->stream == pipe_ctx_old->stream) {
 			if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
-				dc->hwss.crtc_switch_to_clk_src(
+				dce_crtc_switch_to_clk_src(dc->hwseq,
 						pipe_ctx->clock_source, i);
 			continue;
 		}
@@ -1990,7 +1962,6 @@  static const struct hw_sequencer_funcs dce110_funcs = {
 	.disable_stream = dce110_disable_stream,
 	.unblank_stream = dce110_unblank_stream,
 	.enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
-	.crtc_switch_to_clk_src = dce110_crtc_switch_to_clk_src,
 	.enable_display_power_gating = dce110_enable_display_power_gating,
 	.power_down_front_end = dce110_power_down_fe,
 	.pipe_control_lock = dce_pipe_control_lock,
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index 3572301e09c0..87ae249779a9 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -425,19 +425,6 @@  static struct stream_encoder *dce110_stream_encoder_create(
 #define SRII(reg_name, block, id)\
 	.reg_name[id] = mm ## block ## id ## _ ## reg_name
 
-#define HWSEQ_DCE11_REG_LIST_BASE() \
-		SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
-		SR(DCFEV_CLOCK_CONTROL), \
-		SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
-		SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
-		SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
-		SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
-		SRII(BLND_V_UPDATE_LOCK, BLND, 0),\
-		SRII(BLND_V_UPDATE_LOCK, BLND, 1),\
-		SRII(BLND_CONTROL, BLND, 0),\
-		SRII(BLND_CONTROL, BLND, 1),\
-		SR(BLNDV_CONTROL)
-
 static const struct dce_hwseq_registers hwseq_stoney_reg = {
 		HWSEQ_ST_REG_LIST()
 };
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
index 1b5182a0c79e..204f613467b7 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_hw_sequencer.c
@@ -66,40 +66,6 @@  static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
 /*******************************************************************************
  * Private definitions
  ******************************************************************************/
-/***************************PIPE_CONTROL***********************************/
-
-static void dce112_crtc_switch_to_clk_src(
-				struct clock_source *clk_src, uint8_t crtc_inst)
-{
-	uint32_t pixel_rate_cntl_value;
-	uint32_t phypll_pixel_rate_cntl_value = 0;
-	uint32_t addr, phypll_addr;
-
-	phypll_addr = mmCRTC0_PHYPLL_PIXEL_RATE_CNTL + crtc_inst *
-		(mmCRTC1_PHYPLL_PIXEL_RATE_CNTL - mmCRTC0_PHYPLL_PIXEL_RATE_CNTL);
-	addr = mmCRTC0_PIXEL_RATE_CNTL + crtc_inst *
-			(mmCRTC1_PIXEL_RATE_CNTL - mmCRTC0_PIXEL_RATE_CNTL);
-
-	pixel_rate_cntl_value = dm_read_reg(clk_src->ctx, addr);
-
-	if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO)
-		set_reg_field_value(pixel_rate_cntl_value, 1,
-			CRTC0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE);
-	else {
-
-		set_reg_field_value(pixel_rate_cntl_value,
-				clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0,
-				CRTC0_PIXEL_RATE_CNTL,
-				CRTC0_PIXEL_RATE_SOURCE);
-
-		set_reg_field_value(phypll_pixel_rate_cntl_value,
-				clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0,
-				CRTC0_PHYPLL_PIXEL_RATE_CNTL,
-				CRTC0_PHYPLL_PIXEL_RATE_SOURCE);
-		dm_write_reg(clk_src->ctx, phypll_addr, phypll_pixel_rate_cntl_value);
-	}
-	dm_write_reg(clk_src->ctx, addr, pixel_rate_cntl_value);
-}
 
 static void dce112_init_pte(struct dc_context *ctx)
 {
@@ -193,7 +159,6 @@  bool dce112_hw_sequencer_construct(struct core_dc *dc)
 	 * structure
 	 */
 	dce110_hw_sequencer_construct(dc);
-	dc->hwss.crtc_switch_to_clk_src = dce112_crtc_switch_to_clk_src;
 	dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
 
 	return true;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index 514669153910..634541eb55c5 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -476,7 +476,7 @@  static struct stream_encoder *dce112_stream_encoder_create(
 	.reg_name[id] = mm ## block ## id ## _ ## reg_name
 
 static const struct dce_hwseq_registers hwseq_reg = {
-		HWSEQ_COMMON_REG_LIST_BASE()
+		HWSEQ_DCE112_REG_LIST()
 };
 
 static const struct dce_hwseq_shift hwseq_shift = {
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
index e568ed891a06..16b10dca6e58 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/hw_sequencer.h
@@ -96,8 +96,6 @@  struct hw_sequencer_funcs {
 	void (*encoder_set_lcd_backlight_level)(
 		struct link_encoder *enc, uint32_t level);
 
-	void (*crtc_switch_to_clk_src)(struct clock_source *, uint8_t);
-
 	void (*enable_display_pipe_clock_gating)(
 					struct dc_context *ctx,
 					bool clock_gating);