[08/14] Backend: Change the sel ir optimization for unpack register

Submitted by Pan Xiuli on Oct. 12, 2016, 8:56 a.m.

Details

Message ID 1476262604-27504-8-git-send-email-xiuli.pan@intel.com
State New
Headers show
Series "Series without cover letter" ( rev: 1 ) in Beignet

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Commit Message

Pan Xiuli Oct. 12, 2016, 8:56 a.m.
From: Pan Xiuli <xiuli.pan@intel.com>

To unpack UW we may need to add mov and we do not want this mov to be
optimizated by the sel ir optimization. Add check for hstrid to avoid
this kind optimization.

Signed-off-by: Pan Xiuli <xiuli.pan@intel.com>
---
 backend/src/backend/gen_insn_selection_optimize.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

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diff --git a/backend/src/backend/gen_insn_selection_optimize.cpp b/backend/src/backend/gen_insn_selection_optimize.cpp
index b8aa776..56c7615 100644
--- a/backend/src/backend/gen_insn_selection_optimize.cpp
+++ b/backend/src/backend/gen_insn_selection_optimize.cpp
@@ -161,7 +161,7 @@  namespace gbe
     assert(insn.opcode == SEL_OP_MOV);
     const GenRegister& src = insn.src(0);
     const GenRegister& dst = insn.dst(0);
-    if (src.type != dst.type || src.file != dst.file)
+    if (src.type != dst.type || src.file != dst.file || src.hstride != dst.hstride)
       return;
 
     if (liveout.find(dst.reg()) != liveout.end())