drm/amdgpu:fix exclusive mode game texture blank(v2)

Submitted by Zhang, Hawking on Sept. 30, 2016, 6:03 a.m.

Details

Message ID BN6PR12MB1204D14D26407231BAE4C98FFCC10@BN6PR12MB1204.namprd12.prod.outlook.com
State New
Headers show
Series "drm/amdgpu:fix exclusive mode game texture blank(v2)" ( rev: 2 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Zhang, Hawking Sept. 30, 2016, 6:03 a.m.
+	if (job && !job->vm_needs_flush && ring->type == AMDGPU_RING_TYPE_GFX) {
+		extra_nop = 128;
+	}
+
Please remove the redundant braces here. With that fixed, the patch is
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>


Regards,
Hawking

-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Monk Liu

Sent: Friday, September 30, 2016 13:00
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: [PATCH] drm/amdgpu:fix exclusive mode game texture blank(v2)

this fix DOTA and other exclusive & full screen game textrue blank bug, the root cause is that when no ctx switch between two DMAframe, CE go too faster and step to the next DMAframe, thus DE and CE are not working on the same DAMframe.

Change-Id: I92714a1d434bb05e94220a2db9b4a6113b0c2efc
Signed-off-by: Monk Liu <Monk.Liu@amd.com>

---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 7 +++++++
 1 file changed, 7 insertions(+)

 		patch_offset = amdgpu_ring_init_cond_exec(ring);
 
 	if (vm) {
+		amdgpu_ring_insert_nop(ring, extra_nop); /* prevent CE go too fast 
+than DE */
+
 		r = amdgpu_vm_flush(ring, job);
 		if (r) {
 			amdgpu_ring_undo(ring);
--
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 38261a0..4863426 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -129,6 +129,7 @@  int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 
 	unsigned i;
 	int r = 0;
+	unsigned extra_nop = 0;
 
 	if (num_ibs == 0)
 		return -EINVAL;
@@ -155,6 +156,10 @@  int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	alloc_size = amdgpu_ring_get_dma_frame_size(ring) +
 		num_ibs * amdgpu_ring_get_emit_ib_size(ring);
 
+	if (job && !job->vm_needs_flush && ring->type == AMDGPU_RING_TYPE_GFX) {
+		extra_nop = 128;
+	}
+
 	r = amdgpu_ring_alloc(ring, alloc_size);
 	if (r) {
 		dev_err(adev->dev, "scheduling IB failed (%d).\n", r); @@ -165,6 +170,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,