[8/9] drm/amdgpu:wptr poll address of gfx8 is needed

Submitted by Deucher, Alexander on Sept. 28, 2016, 3:27 p.m.

Details

Message ID MWHPR12MB169469DF6CB1A70E185D0563F7CF0@MWHPR12MB1694.namprd12.prod.outlook.com
State New
Headers show
Series "Series without cover letter" ( rev: 2 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Deucher, Alexander Sept. 28, 2016, 3:27 p.m.
Worth a shot, but I doubt it.  Wptr polling is only enabled if explicitly requested.  I'm not sure if CP PG will work without doorbells since the doorbells are handled by the BIF and forwarded to the CP which should wake it if it's gated.  Wptr polling may require CP PG be disabled or prevent it from kicking in.  Probably want to ask the CP team.

Alex

From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of StDenis, Tom
Sent: Wednesday, September 28, 2016 9:41 AM
To: Liu, Monk; amd-gfx@lists.freedesktop.org
Cc: Min, Frank
Subject: Re: [PATCH 8/9] drm/amdgpu:wptr poll address of gfx8 is needed


Hmm, I wonder if this fix CP power gating issues ... on Carrizo/Stoney...

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 097108a..98ef1fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4338,7 +4338,7 @@  static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
         struct amdgpu_ring *ring;
         u32 tmp;
         u32 rb_bufsz;
-       u64 rb_addr, rptr_addr;
+       u64 rb_addr, rptr_addr, wptr_gpu_addr;
         int r;

         /* Set the write pointer delay */
@@ -4369,6 +4369,9 @@  static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);

+       wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
+       WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
         mdelay(1);
         WREG32(mmCP_RB0_CNTL, tmp);