[8/9] drm/amdgpu:wptr poll address of gfx8 is needed

Submitted by StDenis, Tom on Sept. 28, 2016, 1:41 p.m.

Details

Message ID CY4PR12MB17686C79F11C47CC29E00E2EF7CF0@CY4PR12MB1768.namprd12.prod.outlook.com
State New
Headers show
Series "Series without cover letter" ( rev: 2 1 ) in AMD X.Org drivers

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Commit Message

StDenis, Tom Sept. 28, 2016, 1:41 p.m.
Hmm, I wonder if this fix CP power gating issues ... on Carrizo/Stoney...

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diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 097108a..98ef1fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4338,7 +4338,7 @@  static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
         struct amdgpu_ring *ring;
         u32 tmp;
         u32 rb_bufsz;
-       u64 rb_addr, rptr_addr;
+       u64 rb_addr, rptr_addr, wptr_gpu_addr;
         int r;

         /* Set the write pointer delay */
@@ -4369,6 +4369,9 @@  static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);

+       wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+       WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
+       WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
         mdelay(1);
         WREG32(mmCP_RB0_CNTL, tmp);