[11/14] drm/amdgpu: fix incorrect index of CG_FFCT_0 register

Submitted by Huang, Ray on Aug. 30, 2016, 11:50 a.m.

Details

Message ID 1472557811-8015-12-git-send-email-ray.huang@amd.com
State New
Headers show
Series "drm/amdgpu/si: Make SI DPM workable" ( rev: 1 ) in AMD X.Org drivers

Not browsing as part of any series.

Commit Message

Huang, Ray Aug. 30, 2016, 11:50 a.m.
Change-Id: I8b1c7618b3043595c1f6d369dca693d4eaac412e
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si_dpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch hide | download patch | download mbox

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index 563aeea..ce563cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -4281,7 +4281,7 @@  static void si_program_tp(struct amdgpu_device *adev)
 	enum r600_td td = R600_TD_DFLT;
 
 	for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
-		WREG32(CG_FFCT_0 + (i * 10), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
+		WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
 
 	if (td == R600_TD_AUTO)
 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);