From patchwork Thu Jan 9 10:29:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [1/6] drm: Introduce sharpness strength property From: Nemesa Garg X-Patchwork-Id: 631659 Message-Id: <20250109102925.1032501-2-nemesa.garg@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Cc: Nemesa Garg Date: Thu, 9 Jan 2025 15:59:20 +0530 Introduces the new crtc property "SHARPNESS_STRENGTH" that allows the user to set the intensity so as to get the sharpness effect. The value of this property can be set from 0-255. It is useful in scenario when the output is blurry and user want to sharpen the pixels. User can increase/decrease the sharpness level depending on the content displayed. v2: Rename crtc property variable [Arun] Add modeset detail in uapi doc[Uma] v3: Fix build issue Signed-off-by: Nemesa Garg --- drivers/gpu/drm/drm_atomic_uapi.c | 4 ++++ drivers/gpu/drm/drm_crtc.c | 35 +++++++++++++++++++++++++++++++ include/drm/drm_crtc.h | 17 +++++++++++++++ 3 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 370dc676e3aa..b482bc2b5d0a 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -417,6 +417,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, set_out_fence_for_crtc(state->state, crtc, fence_ptr); } else if (property == crtc->scaling_filter_property) { state->scaling_filter = val; + } else if (property == crtc->sharpness_strength_property) { + state->sharpness_strength = val; } else if (crtc->funcs->atomic_set_property) { return crtc->funcs->atomic_set_property(crtc, state, property, val); } else { @@ -454,6 +456,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = 0; else if (property == crtc->scaling_filter_property) *val = state->scaling_filter; + else if (property == crtc->sharpness_strength_property) + *val = state->sharpness_strength; else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else { diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 3488ff067c69..c4a267fa3402 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -229,6 +229,25 @@ struct dma_fence *drm_crtc_create_fence(struct drm_crtc *crtc) * Driver's default scaling filter * Nearest Neighbor: * Nearest Neighbor scaling filter + * SHARPNESS_STRENGTH: + * Atomic property for setting the sharpness strength/intensity by userspace. + * + * The value of this property is set as an integer value ranging + * from 0 - 255 where: + * + * 0 means feature is disabled. + * + * 1 means minimum sharpness. + * + * 255 means maximum sharpness. + * + * User can gradually increase or decrease the sharpness level and can + * set the optimum value depending on content and this value will be + * passed to kernel through the Uapi. + * The setting of this property does not require modeset. + * The sharpness effect takes place post blending on the final composed output. + * If the feature is disabled, the content remains same without any sharpening effect + * and when this feature is applied, it enhances the clarity of the content. */ __printf(6, 0) @@ -939,3 +958,19 @@ int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, return 0; } EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property); + +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_property *prop = + drm_property_create_range(dev, 0, "SHARPNESS_STRENGTH", 0, 255); + + if (!prop) + return -ENOMEM; + + crtc->sharpness_strength_property = prop; + drm_object_attach_property(&crtc->base, prop, 0); + + return 0; +} +EXPORT_SYMBOL(drm_crtc_create_sharpness_strength_property); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 8b48a1974da3..37a879350b4e 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -317,6 +317,16 @@ struct drm_crtc_state { */ enum drm_scaling_filter scaling_filter; + /** + * @sharpness_strength + * + * Used by the user to set the sharpness intensity. + * The value ranges from 0-255. + * Any value greater than 0 means enabling the featuring + * along with setting the value for sharpness. + */ + u8 sharpness_strength; + /** * @event: * @@ -1088,6 +1098,12 @@ struct drm_crtc { */ struct drm_property *scaling_filter_property; + /** + * @sharpness_strength_prop: property to apply + * the intensity of the sharpness requested. + */ + struct drm_property *sharpness_strength_property; + /** * @state: * @@ -1324,4 +1340,5 @@ static inline struct drm_crtc *drm_crtc_find(struct drm_device *dev, int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, unsigned int supported_filters); +int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc); #endif /* __DRM_CRTC_H__ */ From patchwork Thu Jan 9 10:29:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [2/6] drm/i915/display: Compute the scaler filter coefficients From: Nemesa Garg X-Patchwork-Id: 631660 Message-Id: <20250109102925.1032501-3-nemesa.garg@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Cc: Nemesa Garg , Naga Venkata Srikanth V Date: Thu, 9 Jan 2025 15:59:21 +0530 The sharpness property requires the use of one of the scaler so need to set the sharpness scaler coefficient values. These values are based on experiments and vary for different tap value/win size. These values are normalized by taking the sum of all values and then dividing each value with a sum. v2: Fix ifndef header naming issue reported by kernel test robot v3: Rename file name[Arun] Replace array size number with macro[Arun] v4: Correct the register format[Jani] Add brief comment and expalin about file[Jani] Remove coefficient value from crtc_state[Jani] v5: Fix build issue Signed-off-by: Nemesa Garg Reviewed-by: Naga Venkata Srikanth V --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_casf.c | 142 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_casf.h | 16 ++ .../gpu/drm/i915/display/intel_casf_regs.h | 19 +++ drivers/gpu/drm/i915/display/intel_display.c | 3 + .../drm/i915/display/intel_display_types.h | 13 ++ drivers/gpu/drm/xe/Makefile | 1 + 7 files changed, 195 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_casf.c create mode 100644 drivers/gpu/drm/i915/display/intel_casf.h create mode 100644 drivers/gpu/drm/i915/display/intel_casf_regs.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 3dda9f0eda82..6f7f47af894e 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -286,6 +286,7 @@ i915-y += \ display/intel_pmdemand.o \ display/intel_psr.o \ display/intel_quirks.o \ + display/intel_casf.o \ display/intel_sprite.o \ display/intel_sprite_uapi.o \ display/intel_tc.o \ diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c new file mode 100644 index 000000000000..b507401457bf --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + * + */ +#include "i915_reg.h" +#include "intel_de.h" +#include "intel_display_types.h" +#include "intel_casf.h" +#include "intel_casf_regs.h" +#include "skl_scaler.h" + +#define FILTER_COEFF_0_125 125 +#define FILTER_COEFF_0_25 250 +#define FILTER_COEFF_0_5 500 +#define FILTER_COEFF_1_0 1000 +#define FILTER_COEFF_0_0 0 +#define SET_POSITIVE_SIGN(x) ((x) & (~SIGN)) + +/** + * DOC: Content Adaptive Sharpness Filter (CASF) + * + * From LNL onwards the display engine based adaptive + * sharpening filter is supported. This helps in + * improving the image quality. The display hardware + * uses one of the pipe scaler for implementing casf. + * It works on a region of pixels depending on the + * tap size. The coefficients are used to generate an + * alpha value which is used to blend the sharpened image + * to original image. + */ + +const u16 filtercoeff_1[] = { + FILTER_COEFF_0_0, FILTER_COEFF_0_0, FILTER_COEFF_0_5, + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_0, + FILTER_COEFF_0_0, + }; + +const u16 filtercoeff_2[] = { + FILTER_COEFF_0_0, FILTER_COEFF_0_25, FILTER_COEFF_0_5, + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, + FILTER_COEFF_0_0, + }; + +const u16 filtercoeff_3[] = { + FILTER_COEFF_0_125, FILTER_COEFF_0_25, FILTER_COEFF_0_5, + FILTER_COEFF_1_0, FILTER_COEFF_0_5, FILTER_COEFF_0_25, + FILTER_COEFF_0_125, + }; + +static int casf_coef_tap(int i) +{ + return i % 7; +} + +static u16 casf_coef(struct intel_crtc_state *crtc_state, int t) +{ + struct scaler_filter_coeff value; + u16 coeff; + + value = crtc_state->hw.casf_params.coeff[t]; + coeff = SET_POSITIVE_SIGN(0) | EXPONENT(value.exp) | MANTISSA(value.mantissa); + + return coeff; +} + +static void intel_casf_write_coeff(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + int id = crtc_state->scaler_state.scaler_id; + int i; + + intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 0), + PS_COEF_INDEX_AUTO_INC); + + intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(crtc->pipe, id, 1), + PS_COEF_INDEX_AUTO_INC); + + for (i = 0; i < 17 * 7; i += 2) { + u32 tmp; + int t; + + t = casf_coef_tap(i); + tmp = casf_coef(crtc_state, t); + + t = casf_coef_tap(i + 1); + tmp |= casf_coef(crtc_state, t) << 16; + + intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 0), + tmp); + intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(crtc->pipe, id, 1), + tmp); + } +} + +void intel_casf_enable(struct intel_crtc_state *crtc_state) +{ + intel_casf_write_coeff(crtc_state); +} + +static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff, + u16 coefficient) +{ + if (coefficient < 25) { + coeff->mantissa = (coefficient * 2048) / 100; + coeff->exp = 3; + } else if (coefficient < 50) { + coeff->mantissa = (coefficient * 1024) / 100; + coeff->exp = 2; + } else if (coefficient < 100) { + coeff->mantissa = (coefficient * 512) / 100; + coeff->exp = 1; + } else { + coeff->mantissa = (coefficient * 256) / 100; + coeff->exp = 0; + } +} + +void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state) +{ + const u16 *filtercoeff; + u16 filter_coeff[SCALER_FILTER_NUM_TAPS]; + u16 sumcoeff = 0; + u8 i; + + if (crtc_state->hw.casf_params.win_size == 0) + filtercoeff = filtercoeff_1; + else if (crtc_state->hw.casf_params.win_size == 1) + filtercoeff = filtercoeff_2; + else + filtercoeff = filtercoeff_3; + + for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) + sumcoeff += *(filtercoeff + i); + + for (i = 0; i < SCALER_FILTER_NUM_TAPS; i++) { + filter_coeff[i] = (*(filtercoeff + i) * 100 / sumcoeff); + convert_sharpness_coef_binary(&crtc_state->hw.casf_params.coeff[i], + filter_coeff[i]); + } +} diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h new file mode 100644 index 000000000000..8e0b67a2fd99 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_CASF_H__ +#define __INTEL_CASF_H__ + +#include + +struct intel_crtc_state; + +void intel_casf_enable(struct intel_crtc_state *crtc_state); +void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state); + +#endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h new file mode 100644 index 000000000000..0b3fcdb22c0c --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_CASF_REGS_H__ +#define __INTEL_CASF_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* Scaler Coefficient structure */ +#define SIGN REG_BIT(15) +#define EXPONENT_MASK REG_GENMASK(13, 12) +#define EXPONENT(x) REG_FIELD_PREP(EXPONENT_MASK, (x)) +#define MANTISSA_MASK REG_GENMASK(11, 3) +#define MANTISSA(x) REG_FIELD_PREP(MANTISSA_MASK, (x)) + +#endif /* __INTEL_CASF_REGS__ */ + diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4271da219b41..413b7fd7e287 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -111,6 +111,7 @@ #include "intel_psr.h" #include "intel_psr_regs.h" #include "intel_sdvo.h" +#include "intel_casf.h" #include "intel_snps_phy.h" #include "intel_tc.h" #include "intel_tdf.h" @@ -6176,6 +6177,8 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state) if (ret) return ret; + intel_casf_scaler_compute_config(new_crtc_state); + /* * On some platforms the number of active planes affects * the planes' minimum cdclk calculation. Add such planes diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index eb9dd1125a4a..4de57ebd12fd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -929,6 +929,18 @@ struct intel_csc_matrix { u16 postoff[3]; }; +struct scaler_filter_coeff { + u16 sign; + u16 exp; + u16 mantissa; +}; + +struct intel_casf { +#define SCALER_FILTER_NUM_TAPS 7 + struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS]; + u8 win_size; +}; + void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val); typedef void (*intel_io_reg_write)(void *ctx, i915_reg_t reg, u32 val); @@ -969,6 +981,7 @@ struct intel_crtc_state { struct drm_property_blob *degamma_lut, *gamma_lut, *ctm; struct drm_display_mode mode, pipe_mode, adjusted_mode; enum drm_scaling_filter scaling_filter; + struct intel_casf casf_params; } hw; /* actual state of LUTs */ diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 5c97ad6ed738..fca8cdb70ce6 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -262,6 +262,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_psr.o \ i915-display/intel_qp_tables.o \ i915-display/intel_quirks.o \ + i915-display/intel_casf.o \ i915-display/intel_snps_phy.o \ i915-display/intel_tc.o \ i915-display/intel_vblank.o \ From patchwork Thu Jan 9 10:29:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [3/6] drm/i915/display: Configure the scaler From: Nemesa Garg X-Patchwork-Id: 631661 Message-Id: <20250109102925.1032501-4-nemesa.garg@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Cc: Nemesa Garg Date: Thu, 9 Jan 2025 15:59:22 +0530 Write the scaler registers for sharpness. Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_casf.c | 2 + drivers/gpu/drm/i915/display/skl_scaler.c | 45 ++++++++++++++++++++++- drivers/gpu/drm/i915/display/skl_scaler.h | 1 + 3 files changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c index b507401457bf..a68860e0acbe 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.c +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -97,6 +97,8 @@ static void intel_casf_write_coeff(struct intel_crtc_state *crtc_state) void intel_casf_enable(struct intel_crtc_state *crtc_state) { intel_casf_write_coeff(crtc_state); + + skl_scaler_setup_casf(crtc_state); } static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff, diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index ae21fce534dc..722d61959bb1 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -98,7 +98,12 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) #define MTL_MAX_DST_H 8192 #define SKL_MIN_YUV_420_SRC_W 16 #define SKL_MIN_YUV_420_SRC_H 16 - +#define SCALER_FILTER_SELECT \ + (PS_FILTER_PROGRAMMED | \ + PS_Y_VERT_FILTER_SELECT(1) | \ + PS_Y_HORZ_FILTER_SELECT(0) | \ + PS_UV_VERT_FILTER_SELECT(1) | \ + PS_UV_HORZ_FILTER_SELECT(0)) static int skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, unsigned int scaler_user, int *scaler_id, @@ -655,6 +660,44 @@ static void skl_scaler_setup_filter(struct intel_display *display, enum pipe pip } } +void skl_scaler_setup_casf(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_display *display = to_intel_display(crtc); + struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + struct intel_crtc_scaler_state *scaler_state = + &crtc_state->scaler_state; + struct drm_rect src, dest; + int id, width, height; + int x, y; + enum pipe pipe = crtc->pipe; + u32 ps_ctrl; + + width = adjusted_mode->crtc_hdisplay; + height = adjusted_mode->crtc_vdisplay; + + x = y = 0; + drm_rect_init(&dest, x, y, width, height); + + width = drm_rect_width(&dest); + height = drm_rect_height(&dest); + id = scaler_state->scaler_id; + + drm_rect_init(&src, 0, 0, + drm_rect_width(&crtc_state->pipe_src) << 16, + drm_rect_height(&crtc_state->pipe_src) << 16); + + ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode | + SCALER_FILTER_SELECT; + + intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl); + intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id), + PS_WIN_XPOS(x) | PS_WIN_YPOS(y)); + intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id), + PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height)); +} + void skl_pfit_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h index 4d2e2dbb1666..e1fe6a2d6c32 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.h +++ b/drivers/gpu/drm/i915/display/skl_scaler.h @@ -28,5 +28,6 @@ void skl_detach_scalers(const struct intel_crtc_state *crtc_state); void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); void skl_scaler_get_config(struct intel_crtc_state *crtc_state); +void skl_scaler_setup_casf(struct intel_crtc_state *crtc_state); #endif From patchwork Thu Jan 9 10:29:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [4/6] drm/i915/display: Enable the second scaler for sharpness From: Nemesa Garg X-Patchwork-Id: 631662 Message-Id: <20250109102925.1032501-5-nemesa.garg@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Cc: Nemesa Garg Date: Thu, 9 Jan 2025 15:59:23 +0530 As only second scaler can be used for sharpness check if it is available and also check if panel fitting is also not enabled, then set the sharpness. Panel fitting will have the preference over sharpness property. v2: Add the panel fitting check before enabling sharpness v3: Reframe commit message[Arun] v4: Replace string based comparison with plane_state[Jani] v5: Rebase v6: Fix build issue Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_casf.c | 7 ++++ drivers/gpu/drm/i915/display/intel_casf.h | 1 + drivers/gpu/drm/i915/display/intel_display.c | 8 ++-- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_pfit.c | 6 +++ drivers/gpu/drm/i915/display/skl_scaler.c | 41 +++++++++++++------ 6 files changed, 49 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c index a68860e0acbe..9a5670de014b 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.c +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -101,6 +101,13 @@ void intel_casf_enable(struct intel_crtc_state *crtc_state) skl_scaler_setup_casf(crtc_state); } +int intel_casf_compute_config(struct intel_crtc_state *crtc_state) +{ + crtc_state->hw.casf_params.need_scaler = true; + + return 0; +} + static void convert_sharpness_coef_binary(struct scaler_filter_coeff *coeff, u16 coefficient) { diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h index 8e0b67a2fd99..568e0f8083eb 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.h +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -12,5 +12,6 @@ struct intel_crtc_state; void intel_casf_enable(struct intel_crtc_state *crtc_state); void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state); +int intel_casf_compute_config(struct intel_crtc_state *crtc_state); #endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 413b7fd7e287..beef3a76eba4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2137,7 +2137,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); if (crtc_state->pch_pfit.enabled || - crtc_state->pch_pfit.force_thru) + crtc_state->pch_pfit.force_thru || crtc_state->hw.casf_params.need_scaler) set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); drm_for_each_encoder_mask(encoder, &dev_priv->drm, @@ -2386,7 +2386,7 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) * PF-ID we'll need to adjust the pixel_rate here. */ - if (!crtc_state->pch_pfit.enabled) + if (!crtc_state->pch_pfit.enabled || crtc_state->hw.casf_params.need_scaler) return pixel_rate; drm_rect_init(&src, 0, 0, @@ -4584,7 +4584,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) >= 9) { if (intel_crtc_needs_modeset(crtc_state) || - intel_crtc_needs_fastset(crtc_state)) { + intel_crtc_needs_fastset(crtc_state) || + crtc_state->hw.casf_params.need_scaler) { ret = skl_update_scaler_crtc(crtc_state); if (ret) return ret; @@ -5750,6 +5751,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); PIPE_CONF_CHECK_BOOL(cmrr.enable); + PIPE_CONF_CHECK_BOOL(hw.casf_params.need_scaler); } #undef PIPE_CONF_CHECK_X diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4de57ebd12fd..6ccfeb1c5462 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -939,6 +939,7 @@ struct intel_casf { #define SCALER_FILTER_NUM_TAPS 7 struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS]; u8 win_size; + bool need_scaler; }; void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val); diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c index 50861aa78a89..cee7c984e66b 100644 --- a/drivers/gpu/drm/i915/display/intel_pfit.c +++ b/drivers/gpu/drm/i915/display/intel_pfit.c @@ -183,6 +183,9 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state, struct intel_display *display = to_intel_display(crtc_state); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); int pipe_src_h = drm_rect_height(&crtc_state->pipe_src); int ret, x, y, width, height; @@ -193,6 +196,9 @@ static int pch_panel_fitting(struct intel_crtc_state *crtc_state, crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) return 0; + if (old_crtc_state->hw.casf_params.need_scaler) + return -EINVAL; + switch (conn_state->scaling_mode) { case DRM_MODE_SCALE_CENTER: width = pipe_src_w; diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index 722d61959bb1..57396f610c89 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -259,7 +259,8 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) drm_rect_width(&crtc_state->pipe_src), drm_rect_height(&crtc_state->pipe_src), width, height, NULL, 0, - crtc_state->pch_pfit.enabled); + crtc_state->pch_pfit.enabled || + crtc_state->hw.casf_params.need_scaler); } /** @@ -298,7 +299,9 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, } static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state, - struct intel_crtc *crtc) + struct intel_crtc *crtc, + struct intel_plane_state *plane_state, + bool casf_scaler) { int i; @@ -306,6 +309,11 @@ static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state, if (scaler_state->scalers[i].in_use) continue; + if (!plane_state) { + if (casf_scaler && i != 1) + continue; + } + scaler_state->scalers[i].in_use = true; return i; @@ -318,19 +326,23 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat int num_scalers_need, struct intel_crtc *crtc, const char *name, int idx, struct intel_plane_state *plane_state, - int *scaler_id) + int *scaler_id, bool casf_scaler) { struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); u32 mode; if (*scaler_id < 0) - *scaler_id = intel_allocate_scaler(scaler_state, crtc); + *scaler_id = intel_allocate_scaler(scaler_state, crtc, plane_state, casf_scaler); if (drm_WARN(display->drm, *scaler_id < 0, "Cannot find scaler for %s:%d\n", name, idx)) return -EINVAL; + if (crtc_state->hw.casf_params.need_scaler) + mode = SKL_PS_SCALER_MODE_HQ; + /* set scaler mode */ if (plane_state && plane_state->hw.fb && plane_state->hw.fb->format->is_yuv && @@ -449,7 +461,8 @@ static int setup_crtc_scaler(struct intel_atomic_state *state, return intel_atomic_setup_scaler(scaler_state, hweight32(scaler_state->scaler_users), crtc, "CRTC", crtc->base.base.id, - NULL, &scaler_state->scaler_id); + NULL, &scaler_state->scaler_id, + crtc_state->hw.casf_params.need_scaler); } static int setup_plane_scaler(struct intel_atomic_state *state, @@ -484,7 +497,8 @@ static int setup_plane_scaler(struct intel_atomic_state *state, return intel_atomic_setup_scaler(scaler_state, hweight32(scaler_state->scaler_users), crtc, "PLANE", plane->base.base.id, - plane_state, &plane_state->scaler_id); + plane_state, &plane_state->scaler_id, + crtc_state->hw.casf_params.need_scaler); } /** @@ -868,16 +882,19 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) continue; id = i; - crtc_state->pch_pfit.enabled = true; + + if (!crtc_state->hw.casf_params.need_scaler) + crtc_state->pch_pfit.enabled = true; pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i)); size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i)); - drm_rect_init(&crtc_state->pch_pfit.dst, - REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), - REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), - REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), - REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); + if (!crtc_state->hw.casf_params.need_scaler) + drm_rect_init(&crtc_state->pch_pfit.dst, + REG_FIELD_GET(PS_WIN_XPOS_MASK, pos), + REG_FIELD_GET(PS_WIN_YPOS_MASK, pos), + REG_FIELD_GET(PS_WIN_XSIZE_MASK, size), + REG_FIELD_GET(PS_WIN_YSIZE_MASK, size)); scaler_state->scalers[i].in_use = true; break; From patchwork Thu Jan 9 10:29:24 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [5/6] drm/i915/display: Add registers and compute the strength From: Nemesa Garg X-Patchwork-Id: 631663 Message-Id: <20250109102925.1032501-6-nemesa.garg@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Cc: Nemesa Garg Date: Thu, 9 Jan 2025 15:59:24 +0530 Add new registers and related bits. Compute the strength value and tap value based on display mode. v2: Replace i915/dev_priv with display[Jani] v3: Create separate file for defining register[Jani] Add display->drm in debug prints[Jani] v4: Rebase v5: Fix build issue Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_casf.c | 114 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_casf.h | 6 + .../gpu/drm/i915/display/intel_casf_regs.h | 20 +++ drivers/gpu/drm/i915/display/intel_display.c | 4 +- 4 files changed, 143 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c index 9a5670de014b..1cca29e1f0eb 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.c +++ b/drivers/gpu/drm/i915/display/intel_casf.c @@ -17,6 +17,9 @@ #define FILTER_COEFF_0_0 0 #define SET_POSITIVE_SIGN(x) ((x) & (~SIGN)) +#define MAX_PIXELS_FOR_3_TAP_FILTER (1920 * 1080) +#define MAX_PIXELS_FOR_5_TAP_FILTER (3840 * 2160) + /** * DOC: Content Adaptive Sharpness Filter (CASF) * @@ -64,6 +67,90 @@ static u16 casf_coef(struct intel_crtc_state *crtc_state, int t) return coeff; } +/* Default LUT values to be loaded one time. */ +static const u16 lut_data[] = { + 4095, 2047, 1364, 1022, 816, 678, 579, + 504, 444, 397, 357, 323, 293, 268, 244, 224, + 204, 187, 170, 154, 139, 125, 111, 98, 85, + 73, 60, 48, 36, 24, 12, 0 +}; + +void intel_filter_lut_load(struct intel_crtc *crtc, + const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + int i; + + intel_de_write(display, SHRPLUT_INDEX(crtc->pipe), + INDEX_AUTO_INCR | INDEX_VALUE(0)); + + for (i = 0; i < ARRAY_SIZE(lut_data); i++) + intel_de_write(display, SHRPLUT_DATA(crtc->pipe), + lut_data[i]); +} + +static void intel_casf_size_compute(struct intel_crtc_state *crtc_state) +{ + const struct drm_display_mode *mode = &crtc_state->hw.adjusted_mode; + u16 total_pixels = mode->hdisplay * mode->vdisplay; + + if (total_pixels <= MAX_PIXELS_FOR_3_TAP_FILTER) + crtc_state->hw.casf_params.win_size = 0; + else if (total_pixels <= MAX_PIXELS_FOR_5_TAP_FILTER) + crtc_state->hw.casf_params.win_size = 1; + else + crtc_state->hw.casf_params.win_size = 2; +} + +bool intel_casf_strength_changed(struct intel_atomic_state *state) +{ + int i; + struct intel_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_crtc *crtc; + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if (new_crtc_state->uapi.sharpness_strength != + old_crtc_state->uapi.sharpness_strength) + return true; + } + + return false; +} + +static void intel_casf_write_reg(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + u32 sharpness_ctl; + u8 val; + + if (crtc_state->uapi.sharpness_strength == 0 || + crtc_state->pch_pfit.enabled) { + intel_casf_disable(crtc_state); + + return; + } + + /* + * HW takes a value in form (1.0 + strength) in 4.4 fixed format. + * Strength is from 0.0-14.9375 ie from 0-239. + * User can give value from 0-255 but is clamped to 239. + * Ex. User gives 85 which is 5.3125 and adding 1.0 gives 6.3125. + * 6.3125 in 4.4 format is 01100101 which is equal to 101. + * Also 85 + 16 = 101. + */ + val = min(crtc_state->uapi.sharpness_strength, 0xEF) + 0x10; + + drm_dbg(display->drm, "Filter strength value: %d\n", val); + + sharpness_ctl = FILTER_EN | FILTER_STRENGTH(val) | + FILTER_SIZE(crtc_state->hw.casf_params.win_size); + + intel_de_write(display, SHARPNESS_CTL(crtc->pipe), + sharpness_ctl); +} + static void intel_casf_write_coeff(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -96,6 +183,8 @@ static void intel_casf_write_coeff(struct intel_crtc_state *crtc_state) void intel_casf_enable(struct intel_crtc_state *crtc_state) { + intel_casf_write_reg(crtc_state); + intel_casf_write_coeff(crtc_state); skl_scaler_setup_casf(crtc_state); @@ -103,8 +192,24 @@ void intel_casf_enable(struct intel_crtc_state *crtc_state) int intel_casf_compute_config(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); + + if (crtc_state->uapi.sharpness_strength == 0) { + crtc_state->hw.casf_params.need_scaler = false; + return 0; + } + + if (crtc_state->pch_pfit.enabled) + return -EINVAL; + crtc_state->hw.casf_params.need_scaler = true; + intel_casf_size_compute(crtc_state); + drm_dbg(display->drm, "Tap Size: %d\n", + crtc_state->hw.casf_params.win_size); + + intel_casf_scaler_compute_config(crtc_state); + return 0; } @@ -149,3 +254,12 @@ void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state) filter_coeff[i]); } } + +void intel_casf_disable(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + intel_de_write(display, SHARPNESS_CTL(crtc->pipe), 0); + drm_dbg(display->drm, "Filter strength value: %d\n", 0); +} diff --git a/drivers/gpu/drm/i915/display/intel_casf.h b/drivers/gpu/drm/i915/display/intel_casf.h index 568e0f8083eb..6e6e6db39613 100644 --- a/drivers/gpu/drm/i915/display/intel_casf.h +++ b/drivers/gpu/drm/i915/display/intel_casf.h @@ -9,9 +9,15 @@ #include struct intel_crtc_state; +struct intel_atomic_state; +struct intel_crtc; void intel_casf_enable(struct intel_crtc_state *crtc_state); void intel_casf_scaler_compute_config(struct intel_crtc_state *crtc_state); int intel_casf_compute_config(struct intel_crtc_state *crtc_state); +void intel_filter_lut_load(struct intel_crtc *crtc, + const struct intel_crtc_state *crtc_state); +bool intel_casf_strength_changed(struct intel_atomic_state *state); +void intel_casf_disable(struct intel_crtc_state *crtc_state); #endif /* __INTEL_CASF_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h b/drivers/gpu/drm/i915/display/intel_casf_regs.h index 0b3fcdb22c0c..b4be252a9671 100644 --- a/drivers/gpu/drm/i915/display/intel_casf_regs.h +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h @@ -15,5 +15,25 @@ #define MANTISSA_MASK REG_GENMASK(11, 3) #define MANTISSA(x) REG_FIELD_PREP(MANTISSA_MASK, (x)) +#define _SHARPNESS_CTL_A 0x682B0 +#define _SHARPNESS_CTL_B 0x68AB0 +#define SHARPNESS_CTL(pipe) _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B) +#define FILTER_EN REG_BIT(31) +#define FILTER_STRENGTH_MASK REG_GENMASK(15, 8) +#define FILTER_STRENGTH(x) REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x)) +#define FILTER_SIZE_MASK REG_GENMASK(1, 0) +#define FILTER_SIZE(x) REG_FIELD_PREP(FILTER_SIZE_MASK, (x)) + +#define _SHRPLUT_DATA_A 0x682B8 +#define _SHRPLUT_DATA_B 0x68AB8 +#define SHRPLUT_DATA(pipe) _MMIO_PIPE(pipe, _SHRPLUT_DATA_A, _SHRPLUT_DATA_B) + +#define _SHRPLUT_INDEX_A 0x682B4 +#define _SHRPLUT_INDEX_B 0x68AB4 +#define SHRPLUT_INDEX(pipe) _MMIO_PIPE(pipe, _SHRPLUT_INDEX_A, _SHRPLUT_INDEX_B) +#define INDEX_AUTO_INCR REG_BIT(10) +#define INDEX_VALUE_MASK REG_GENMASK(4, 0) +#define INDEX_VALUE(x) REG_FIELD_PREP(INDEX_VALUE_MASK, (x)) + #endif /* __INTEL_CASF_REGS__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index beef3a76eba4..67dfd428d85f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6179,7 +6179,9 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state) if (ret) return ret; - intel_casf_scaler_compute_config(new_crtc_state); + ret = intel_casf_compute_config(new_crtc_state); + if (ret) + return ret; /* * On some platforms the number of active planes affects From patchwork Thu Jan 9 10:29:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [6/6] drm/i915/display: Load the lut values and enable sharpness From: Nemesa Garg X-Patchwork-Id: 631664 Message-Id: <20250109102925.1032501-7-nemesa.garg@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Cc: Nemesa Garg , Naga Venkata Srikanth V Date: Thu, 9 Jan 2025 15:59:25 +0530 Load the lut values during pipe enable. v2: Add the display version check v3: Fix build issue Signed-off-by: Nemesa Garg Reviewed-by: Naga Venkata Srikanth V --- drivers/gpu/drm/i915/display/intel_crtc.c | 3 +++ drivers/gpu/drm/i915/display/intel_display.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/skl_scaler.c | 14 +++++++++++++- 4 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index c910168602d2..f502530a98af 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -389,6 +389,9 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); + if (DISPLAY_VER(dev_priv) >= 20) + drm_crtc_create_sharpness_strength_property(&crtc->base); + return 0; fail: diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 67dfd428d85f..429022b6788b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1881,6 +1881,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_crtc_wait_for_next_vblank(wa_crtc); } } + + if (new_crtc_state->hw.casf_params.strength_changed) + intel_filter_lut_load(crtc, new_crtc_state); } void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) @@ -7182,6 +7185,9 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_vrr_set_transcoder_timings(new_crtc_state); } + if (intel_casf_strength_changed(state)) + intel_casf_enable(new_crtc_state); + intel_fbc_update(state, crtc); drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 6ccfeb1c5462..cf7f4aebd6fa 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -940,6 +940,8 @@ struct intel_casf { struct scaler_filter_coeff coeff[SCALER_FILTER_NUM_TAPS]; u8 win_size; bool need_scaler; + bool strength_changed; + u8 strength; }; void intel_io_mmio_fw_write(void *ctx, i915_reg_t reg, u32 val); diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index 57396f610c89..01b1cbaae28f 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -8,6 +8,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_fb.h" +#include "intel_casf_regs.h" #include "skl_scaler.h" #include "skl_universal_plane.h" @@ -875,7 +876,7 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) /* find scaler attached to this pipe */ for (i = 0; i < crtc->num_scalers; i++) { - u32 ctl, pos, size; + u32 ctl, pos, size, sharp; ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i)); if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE)) @@ -883,6 +884,17 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state) id = i; + if (DISPLAY_VER(display) >= 20) { + sharp = intel_de_read(display, SHARPNESS_CTL(crtc->pipe)); + if (sharp & FILTER_EN) { + crtc_state->hw.casf_params.strength = + REG_FIELD_GET(FILTER_STRENGTH_MASK, sharp) - 16; + crtc_state->hw.casf_params.need_scaler = true; + crtc_state->hw.casf_params.win_size = + REG_FIELD_GET(FILTER_SIZE_MASK, sharp); + } + } + if (!crtc_state->hw.casf_params.need_scaler) crtc_state->pch_pfit.enabled = true;