From patchwork Fri Jun 16 06:30:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [01/16] drm/i915/dp: Remove extra logs for printing DSC info From: Ankit Nautiyal X-Patchwork-Id: 542795 Message-Id: <20230616063053.2158108-3-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:12 +0530 DSC compressed bpp and slice counts are already getting printed at the end of dsc compute config. Remove extra logs. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 80d95cec8f9d..93aebd3683a4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1576,9 +1576,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->pipe_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; - drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", - pipe_config->dsc.compressed_bpp, - pipe_config->dsc.slice_count); } /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate From patchwork Fri Jun 16 06:30:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [02/27] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints From: Ankit Nautiyal X-Patchwork-Id: 542797 Message-Id: <20230616063053.2158108-4-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:13 +0530 Add a wrapper function to check dp_downstream clock/bandwidth constraints. Based on whether the sink supports FRL/TMDS the wrapper calls the appropriate FRL/TMDS functions. v2: Use new wrapper while getting max bpc also. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 54 ++++++++++++------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index abcd7e11b097..e024028701b7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1065,6 +1065,25 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock, return MODE_OK; } +static bool +pcon_sink_pair_support_frl(struct intel_dp *intel_dp) +{ + return intel_dp->dfp.pcon_max_frl_bw && intel_dp_hdmi_sink_max_frl(intel_dp); +} + +static enum drm_mode_status +intel_dp_hdmi_bw_check(struct intel_dp *intel_dp, + int target_clock, int bpc, + enum intel_output_format sink_format, + bool respect_downstream_limits) +{ + if (pcon_sink_pair_support_frl(intel_dp)) + return intel_dp_frl_bw_valid(intel_dp, target_clock, bpc, sink_format); + + return intel_dp_tmds_clock_valid(intel_dp, target_clock, bpc, sink_format, + respect_downstream_limits); +} + static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, @@ -1074,42 +1093,23 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_info *info = &connector->base.display_info; enum drm_mode_status status; enum intel_output_format sink_format = intel_dp_sink_format(connector, mode); + int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw check */ - /* If PCON supports FRL MODE, check FRL bandwidth constraints */ - if (intel_dp->dfp.pcon_max_frl_bw && intel_dp_hdmi_sink_max_frl(intel_dp)) { - /* Assume 8bpc for the HDMI2.1 FRL BW check */ - status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); - if (status != MODE_OK) { - if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || - !connector->base.ycbcr_420_allowed || - !drm_mode_is_420_also(info, mode)) - return status; - - sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); - if (status != MODE_OK) - return status; - } - - return MODE_OK; - } - - if (intel_dp->dfp.max_dotclock && + if (!intel_dp_hdmi_sink_max_frl(intel_dp) && + intel_dp->dfp.max_dotclock && target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; - /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ - status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, sink_format, true); + status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, true); if (status != MODE_OK) { if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || !connector->base.ycbcr_420_allowed || !drm_mode_is_420_also(info, mode)) return status; + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, sink_format, true); + status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, true); if (status != MODE_OK) return status; } @@ -1376,8 +1376,8 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, for (; bpc >= 8; bpc -= 2) { if (intel_hdmi_bpc_possible(crtc_state, bpc, intel_dp_has_hdmi_sink(intel_dp)) && - intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, - respect_downstream_limits) == MODE_OK) + intel_dp_hdmi_bw_check(intel_dp, clock, bpc, crtc_state->sink_format, + respect_downstream_limits) == MODE_OK) return bpc; } From patchwork Fri Jun 16 06:30:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [03/27] drm/i915/dp: Consider output_format while computing dsc bpp From: Ankit Nautiyal X-Patchwork-Id: 542798 Message-Id: <20230616063053.2158108-6-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:15 +0530 While using DSC the compressed bpp is computed assuming RGB output format. Consider the output_format and compute the compressed bpp during mode valid and compute config steps. For DP-MST we currently use RGB output format only, so continue using RGB while computing compressed bpp for MST case. v2: Use output_bpp instead for pipe_bpp to clamp compressed_bpp. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e024028701b7..a6994f95bfd3 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -736,6 +736,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, bool bigjoiner, + enum intel_output_format output_format, u32 pipe_bpp, u32 timeslots) { @@ -760,6 +761,10 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, bits_per_pixel = ((link_clock * lane_count) * timeslots) / (intel_dp_mode_to_fec_clock(mode_clock) * 8); + /* Bandwidth required for 420 is half, that of 444 format */ + if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + bits_per_pixel *= 2; + drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots " "total bw %u pixel clock %u\n", bits_per_pixel, timeslots, @@ -1178,11 +1183,16 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (HAS_DSC(dev_priv) && drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + enum intel_output_format sink_format, output_format; + int pipe_bpp; + + sink_format = intel_dp_sink_format(connector, mode); + output_format = intel_dp_output_format(connector, sink_format); /* * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); /* * Output bpp is stored in 6.4 format so right shift by 4 to get the @@ -1202,6 +1212,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, target_clock, mode->hdisplay, bigjoiner, + output_format, pipe_bpp, 64) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, @@ -1741,6 +1752,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes, + pipe_config->output_format, pipe_bpp, timeslots); /* @@ -1776,9 +1788,12 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, * calculation procedure is bit different for MST case. */ if (compute_pipe_bpp) { + u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format, + pipe_config->pipe_bpp); + pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_output_bpp >> 4, - pipe_config->pipe_bpp); + output_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 22099de3ca45..bb4f976af296 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -111,6 +111,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, bool bigjoiner, + enum intel_output_format output_format, u32 pipe_bpp, u32 timeslots); u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e3f176a093d2..aa8d9d570626 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -973,6 +973,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, target_clock, mode->hdisplay, bigjoiner, + INTEL_OUTPUT_FORMAT_RGB, pipe_bpp, 64) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, From patchwork Fri Jun 16 06:30:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [04/16] drm/i915/dp: Check if dsc forced bpc is in allowed limits From: Ankit Nautiyal X-Patchwork-Id: 542801 Message-Id: <20230616063053.2158108-8-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:17 +0530 Add a check to use force DSC bpc only if it, along with the corresponding bpp are within allowed limits. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d061fc3fa402..354dbd1d3164 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1510,19 +1510,20 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, int forced_bpc = intel_dp->force_dsc_bpc; int forced_bpp = forced_bpc * 3; - /* Min Input BPC for ICL+ is 8 */ - if (forced_bpc < 8) { + if (forced_bpc < 8 || /* Min Input BPC for ICL+ is 8 */ + forced_bpc > conn_state->max_requested_bpc || + forced_bpp < limits->min_bpp || + forced_bpp > limits->max_bpp) { drm_dbg_kms(&dev_priv->drm, - "Cannot force dsc bpc:%d, due to dsc bpc limits\n", + "Cannot force dsc bpc:%d, due to bpc/bpp limits\n", intel_dp->force_dsc_bpc); return -EINVAL; } pipe_config->pipe_bpp = forced_bpp; - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", - pipe_config->pipe_bpp); + drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_config->pipe_bpp); } else if (compute_pipe_bpp) { - int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, - conn_state->max_requested_bpc); + int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); + if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) { drm_dbg_kms(&dev_priv->drm, "No DSC support for less than 8bpc\n"); @@ -1530,7 +1531,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, } pipe_config->pipe_bpp = pipe_bpp; } - /* * For now enable DSC for max link rate, max lane count. * Optimize this later for the minimum possible link rate/lane count From patchwork Fri Jun 16 06:30:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [05/16] drm/display/dp: Fix the DP DSC Receiver cap size From: Ankit Nautiyal X-Patchwork-Id: 542803 Message-Id: <20230616063053.2158108-10-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:19 +0530 DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh. Fix the DSC RECEIVER CAP SIZE accordingly. Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT") Cc: Anusha Srivatsa Cc: Manasi Navare Cc: # v5.0+ Reported-by: kernel test robot Signed-off-by: Ankit Nautiyal --- include/drm/display/drm_dp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 632376c291db..bdc05593f462 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -1532,7 +1532,7 @@ enum drm_dp_phy { #define DP_BRANCH_OUI_HEADER_SIZE 0xc #define DP_RECEIVER_CAP_SIZE 0xf -#define DP_DSC_RECEIVER_CAP_SIZE 0xf +#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */ #define EDP_PSR_RECEIVER_CAP_SIZE 2 #define EDP_DISPLAY_CTL_CAP_SIZE 3 #define DP_LTTPR_COMMON_CAP_SIZE 8 From patchwork Fri Jun 16 06:30:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [06/16] drm/display/dp: Add helper function to get DSC bpp prescision From: Ankit Nautiyal X-Patchwork-Id: 542805 Message-Id: <20230616063053.2158108-12-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:21 +0530 Add helper to get the DSC bits_per_pixel precision for the DP sink. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++ include/drm/display/drm_dp_helper.h | 1 + 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index 16565a0a5da6..db3288af4032 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, } EXPORT_SYMBOL(drm_dp_read_desc); +/** + * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment + * @dsc_dpcd: DSC capabilities from DPCD + * + * Returns the bpp precision supported by the DP sink. + */ +u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; + + switch (bpp_increment_dpcd) { + case DP_DSC_BITS_PER_PIXEL_1_16: + return 16; + case DP_DSC_BITS_PER_PIXEL_1_8: + return 8; + case DP_DSC_BITS_PER_PIXEL_1_4: + return 4; + case DP_DSC_BITS_PER_PIXEL_1_2: + return 2; + case DP_DSC_BITS_PER_PIXEL_1_1: + return 1; + } + + return 0; +} +EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr); + /** * drm_dp_dsc_sink_max_slice_count() - Get the max slice count * supported by the DSC sink. diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index ab55453f2d2c..0a0306b2e829 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) } /* DP/eDP DSC support */ +u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], bool is_edp); u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); From patchwork Fri Jun 16 06:30:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [07/16] drm/i915/dp: Avoid left shift of DSC output bpp by 4 From: Ankit Nautiyal X-Patchwork-Id: 542807 Message-Id: <20230616063053.2158108-14-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:23 +0530 To make way for fractional bpp support, avoid left shifting the output_bpp by 4 in helper intel_dp_dsc_get_output_bpp. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 10 +++------- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 354dbd1d3164..c52e9979f0a4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -749,11 +749,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); - /* - * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, - * fractional part is 0 - */ - return bits_per_pixel << 4; + return bits_per_pixel; } u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, @@ -1050,7 +1046,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, target_clock, mode->hdisplay, bigjoiner, - pipe_bpp, 64) >> 4; + pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1585,7 +1581,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, */ if (compute_pipe_bpp) { pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_output_bpp >> 4, + dsc_max_output_bpp, pipe_config->pipe_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 9be04c60cced..5b65e4c2c78f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -921,7 +921,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, target_clock, mode->hdisplay, bigjoiner, - pipe_bpp, 64) >> 4; + pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, From patchwork Fri Jun 16 06:30:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [08/16] drm/i915/dp: Rename helpers to get DSC max pipe_bpp/output_bpp From: Ankit Nautiyal X-Patchwork-Id: 542809 Message-Id: <20230616063053.2158108-17-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:26 +0530 Currently the required dsc output bpp is set to be the largest compressed bpp supported for max, lane, rate, and bpp. The helper intel_dp_dsc_get_output_bpp gets the maximum supported compressed bpp taking into account link configuration, input bpp, bigjoiner considerations etc. Similarly, the helper intel_dp_dsc_compute_bpp gives the maximum pipe bpp that is allowed with DSC. Rename the functions to reflect that these return max DSC input and output bpps. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 48 ++++++++++----------- drivers/gpu/drm/i915/display/intel_dp.h | 14 +++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 +++---- 3 files changed, 39 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c52e9979f0a4..c0b96cfb7528 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -702,12 +702,12 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p return bits_per_pixel; } -u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - u32 pipe_bpp, - u32 timeslots) +u16 intel_dp_dsc_get_output_bpp_max(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots) { u32 bits_per_pixel, max_bpp_small_joiner_ram; @@ -1030,7 +1030,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, U8_MAX); if (intel_dp_is_edp(intel_dp)) { dsc_max_output_bpp = @@ -1040,13 +1040,13 @@ intel_dp_mode_valid(struct drm_connector *_connector, true); } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { dsc_max_output_bpp = - intel_dp_dsc_get_output_bpp(dev_priv, - max_link_clock, - max_lanes, - target_clock, - mode->hdisplay, - bigjoiner, - pipe_bpp, 64); + intel_dp_dsc_get_output_bpp_max(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1375,7 +1375,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return -EINVAL; } -int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) +int intel_dp_dsc_get_bpp_max(struct intel_dp *intel_dp, u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int i, num_bpc; @@ -1518,7 +1518,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->pipe_bpp = forced_bpp; drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_config->pipe_bpp); } else if (compute_pipe_bpp) { - int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); + int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, conn_state->max_requested_bpc); if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) { drm_dbg_kms(&dev_priv->drm, @@ -1548,14 +1548,14 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (compute_pipe_bpp) { dsc_max_output_bpp = - intel_dp_dsc_get_output_bpp(dev_priv, - pipe_config->port_clock, - pipe_config->lane_count, - adjusted_mode->crtc_clock, - adjusted_mode->crtc_hdisplay, - pipe_config->bigjoiner_pipes, - pipe_config->pipe_bpp, - timeslots); + intel_dp_dsc_get_output_bpp_max(dev_priv, + pipe_config->port_clock, + pipe_config->lane_count, + adjusted_mode->crtc_clock, + adjusted_mode->crtc_hdisplay, + pipe_config->bigjoiner_pipes, + pipe_config->pipe_bpp, + timeslots); if (!dsc_max_output_bpp) { drm_dbg_kms(&dev_priv->drm, "Compressed BPP not supported\n"); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index ef39e4f7a329..7cb8227a4d1e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -102,13 +102,13 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); -int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); -u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - u32 pipe_bpp, - u32 timeslots); +int intel_dp_dsc_get_bpp_max(struct intel_dp *intel_dp, u8 dsc_max_bpc); +u16 intel_dp_dsc_get_output_bpp_max(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots); u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, int mode_hdisplay, bool bigjoiner); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 5b65e4c2c78f..df19691776ca 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -911,17 +911,17 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + int pipe_bpp = intel_dp_dsc_get_bpp_max(intel_dp, U8_MAX); if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { dsc_max_output_bpp = - intel_dp_dsc_get_output_bpp(dev_priv, - max_link_clock, - max_lanes, - target_clock, - mode->hdisplay, - bigjoiner, - pipe_bpp, 64); + intel_dp_dsc_get_output_bpp_max(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, From patchwork Fri Jun 16 06:30:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [09/27] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck From: Ankit Nautiyal X-Patchwork-Id: 542811 Message-Id: <20230616063053.2158108-19-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:28 +0530 As per Bsepc:49259, Bigjoiner BW check puts restriction on the compressed bpp for a given CDCLK, pixelclock in cases where Bigjoiner + DSC are used. Currently compressed bpp is computed first, and it is ensured that the bpp will work at least with the max CDCLK freq. Since the CDCLK is computed later, lets account for Bigjoiner BW check while calculating Min CDCLK. v2: Use pixel clock in the bw calculations. (Ville) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_cdclk.c | 51 +++++++++++++++++++--- 1 file changed, 44 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 990dc16511f9..58c1fb773435 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2533,6 +2533,48 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) return min_cdclk; } +static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + int min_cdclk = 0; + + /* + * When we decide to use only one VDSC engine, since + * each VDSC operates with 1 ppc throughput, pixel clock + * cannot be higher than the VDSC clock (cdclk) + */ + if (!crtc_state->dsc.dsc_split) + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); + + if (crtc_state->bigjoiner_pipes) { + int pixel_clock = crtc_state->hw.adjusted_mode.clock; + + /* + * According to Bigjoiner bw check: + * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock + * + * We have already computed compressed_bpp, so now compute the min CDCLK that + * is required to support this compressed_bpp. + * + * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) + * + * Since PPC = 2 with bigjoiner + * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits + * + * #TODO Bspec mentions to account for FEC overhead while using pixel clock. + * Check if we need to use FEC overhead in the above calculations. + */ + int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24; + int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) / + (2 * bigjoiner_interface_bits); + + min_cdclk = max(min_cdclk, min_cdclk_bj); + } + + return min_cdclk; +} + int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = @@ -2604,13 +2646,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) /* Account for additional needs from the planes */ min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); - /* - * When we decide to use only one VDSC engine, since - * each VDSC operates with 1 ppc throughput, pixel clock - * cannot be higher than the VDSC clock (cdclk) - */ - if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split) - min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); + if (crtc_state->dsc.compression_enable) + min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); /* * HACK. Currently for TGL/DG2 platforms we calculate From patchwork Fri Jun 16 06:30:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [10/16] drm/i915/display: Store compressed bpp in U6.4 format From: Ankit Nautiyal X-Patchwork-Id: 542813 Message-Id: <20230616063053.2158108-20-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:29 +0530 DSC parameter bits_per_pixel is stored in U6.4 format. The 4 bits represent the fractional part of the bpp. Currently we use compressed_bpp member of dsc structure to store only the integral part of the bits_per_pixel. To store the full bits_per_pixel along with the fractional part, compressed_bpp is changed to store bpp in U6.4 formats. Intergral part is retrieved by simply right shifting the member compressed_bpp by 4. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++---- drivers/gpu/drm/i915/display/intel_audio.c | 2 +- drivers/gpu/drm/i915/display/intel_bios.c | 2 +- .../drm/i915/display/intel_display_types.h | 16 +++++++++++- drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++-------- drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-- 6 files changed, 38 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index ae14c794c4bc..f387450c4be2 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -343,7 +343,7 @@ static int afe_clk(struct intel_encoder *encoder, int bpp; if (crtc_state->dsc.compression_enable) - bpp = crtc_state->dsc.compressed_bpp; + bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp); else bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); @@ -903,7 +903,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, * compressed and non-compressed bpp. */ if (crtc_state->dsc.compression_enable) { - mul = crtc_state->dsc.compressed_bpp; + mul = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp); div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); } @@ -927,7 +927,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, int bpp, line_time_us, byte_clk_period_ns; if (crtc_state->dsc.compression_enable) - bpp = crtc_state->dsc.compressed_bpp; + bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp); else bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); @@ -1500,8 +1500,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - if (pipe_config->dsc.compressed_bpp) { - int div = pipe_config->dsc.compressed_bpp; + if (dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)) { + int div = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp); int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); adjusted_mode->crtc_htotal = diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 626c47e96a6d..a73cf477b5e6 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -517,7 +517,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; h_total = crtc_state->hw.adjusted_mode.crtc_htotal; pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; - vdsc_bpp = crtc_state->dsc.compressed_bpp; + vdsc_bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp); cdclk = i915->display.cdclk.hw.cdclk; /* fec= 0.972261, using rounding multiplier of 1000000 */ fec_coeff = 972261; diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 78abe34c7a42..75343bca8750 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -3482,7 +3482,7 @@ static void fill_dsc(struct intel_crtc_state *crtc_state, crtc_state->pipe_bpp = bpc * 3; crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, - VBT_DSC_MAX_BPP(dsc->max_bpp)); + VBT_DSC_MAX_BPP(dsc->max_bpp)) << 4; /* * FIXME: This is ugly, and slice count should take DSC engine diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 32e8b2fc3cc6..e879a9483148 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1283,7 +1283,7 @@ struct intel_crtc_state { struct { bool compression_enable; bool dsc_split; - u16 compressed_bpp; + u16 compressed_bpp; /* U6.4 format (first 4 bits for fractional part) */ u8 slice_count; struct drm_dsc_config config; } dsc; @@ -2062,4 +2062,18 @@ to_intel_frontbuffer(struct drm_framebuffer *fb) return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; } +/* Returns integral part of the compressed bpp given in U6.4 format */ +static inline int +dsc_integral_compressed_bpp(u16 compressed_bpp) +{ + return compressed_bpp >> 4; +} + +/* Returns fractional part of the compressed bpp given in U6.4 format */ +static inline int +dsc_fractional_compressed_bpp(u16 compressed_bpp) +{ + return ((compressed_bpp & 0xF) * 10000 / 16); +} + #endif /* __INTEL_DISPLAY_TYPES_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 885d2f75ddbf..ce7bffbdad9e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1606,7 +1606,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, pipe_bpp, compressed_bpp); if (ret == 0) { - pipe_config->dsc.compressed_bpp = compressed_bpp; + pipe_config->dsc.compressed_bpp = compressed_bpp << 4; return 0; } } @@ -1737,8 +1737,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->port_clock = limits->max_rate; pipe_config->lane_count = limits->max_lane_count; pipe_config->dsc.compressed_bpp = - min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, - pipe_config->pipe_bpp); + min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd), + pipe_config->pipe_bpp << 4); } else { /* * For DP compute the optimal pipe bpp, link rate and @@ -1792,17 +1792,19 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (ret < 0) { drm_dbg_kms(&dev_priv->drm, "Cannot compute valid DSC parameters for Input Bpp = %d " - "Compressed BPP = %d\n", + "Compressed BPP = %d.%d\n", pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp); + dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp), + dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp)); return ret; } pipe_config->dsc.compression_enable = true; drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " - "Compressed Bpp = %d Slice Count = %d\n", + "Compressed Bpp = %d.%d Slice Count = %d\n", pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp, + dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp), + dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp), pipe_config->dsc.slice_count); return 0; @@ -1881,15 +1883,16 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, if (pipe_config->dsc.compression_enable) { drm_dbg_kms(&i915->drm, - "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", + "DP lane count %d clock %d Input bpp %d Compressed bpp %d.%d\n", pipe_config->lane_count, pipe_config->port_clock, pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp); + dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp), + dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp)); drm_dbg_kms(&i915->drm, "DP link rate required %i available %i\n", intel_dp_link_required(adjusted_mode->crtc_clock, - pipe_config->dsc.compressed_bpp), + dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)), intel_dp_max_data_rate(pipe_config->port_clock, pipe_config->lane_count)); } else { @@ -2315,7 +2318,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_dp_limited_color_range(pipe_config, conn_state); if (pipe_config->dsc.compression_enable) - output_bpp = pipe_config->dsc.compressed_bpp; + output_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp); else output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_config->pipe_bpp); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 207b2a648d32..ed5c85229414 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -452,7 +452,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; - u16 compressed_bpp = pipe_config->dsc.compressed_bpp; + u16 compressed_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp); const struct rc_parameters *rc_params; struct rc_parameters *rc = NULL; u8 i = 0; @@ -1210,7 +1210,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) val = intel_de_read(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); vdsc_cfg->bits_per_pixel = val; - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel; out: intel_display_power_put(dev_priv, power_domain, wakeref); } From patchwork Fri Jun 16 06:30:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [11/27] drm/display/dp: Fix the DP DSC Receiver cap size From: Ankit Nautiyal X-Patchwork-Id: 542814 Message-Id: <20230616063053.2158108-22-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:31 +0530 DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh. Fix the DSC RECEIVER CAP SIZE accordingly. Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT") Cc: Anusha Srivatsa Cc: Manasi Navare Cc: # v5.0+ Signed-off-by: Ankit Nautiyal --- include/drm/display/drm_dp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 02f2ac4dd2df..e69cece404b3 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -1537,7 +1537,7 @@ enum drm_dp_phy { #define DP_BRANCH_OUI_HEADER_SIZE 0xc #define DP_RECEIVER_CAP_SIZE 0xf -#define DP_DSC_RECEIVER_CAP_SIZE 0xf +#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */ #define EDP_PSR_RECEIVER_CAP_SIZE 2 #define EDP_DISPLAY_CTL_CAP_SIZE 3 #define DP_LTTPR_COMMON_CAP_SIZE 8 From patchwork Fri Jun 16 06:30:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [12/27] drm/i915/dp: Avoid forcing DSC BPC for MST case From: Ankit Nautiyal X-Patchwork-Id: 542817 Message-Id: <20230616063053.2158108-25-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:34 +0530 For MST the bpc is hardcoded to 8, and pipe bpp to 24. So avoid forcing DSC bpc for MST case. v2: Warn and ignore the debug flag than to bail out. (Jani) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------ drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d0c6516cfc6c..125d3a86ede7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1712,14 +1712,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) return -EINVAL; - if (compute_pipe_bpp) + if (intel_dp->force_dsc_bpc && compute_pipe_bpp) { + pipe_bpp = intel_dp->force_dsc_bpc * 3; + drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp); + } else if (compute_pipe_bpp) { pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); - else + } else { pipe_bpp = pipe_config->pipe_bpp; - - if (intel_dp->force_dsc_bpc) { - pipe_bpp = intel_dp->force_dsc_bpc * 3; - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp); } /* Min Input BPC for ICL+ is 8 */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1f00713fb1ad..dff4717edbd0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -361,6 +361,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, /* enable compression if the mode doesn't fit available BW */ drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); if (ret || intel_dp->force_dsc_en) { + /* + * FIXME: As bpc is hardcoded to 8, as mentioned above, + * WARN and ignore the debug flag force_dsc_bpc for now. + */ + drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n"); /* * Try to get at least some timeslots and then see, if * we can fit there with DSC. From patchwork Fri Jun 16 06:30:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [13/27] drm/i915/dp: Add functions to get min/max src input bpc with DSC From: Ankit Nautiyal X-Patchwork-Id: 542819 Message-Id: <20230616063053.2158108-26-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:35 +0530 Separate out functions for getting maximum and minimum input BPC based on platforms, when DSC is used. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 39 ++++++++++++++++++++----- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 125d3a86ede7..7f5b39064f13 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1550,6 +1550,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return -EINVAL; } +static +u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) +{ + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ + if (DISPLAY_VER(i915) >= 12) + return 8; + if (DISPLAY_VER(i915) == 11) + return 10; + + return 0; +} + int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1557,11 +1569,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) u8 dsc_bpc[3] = {0}; u8 dsc_max_bpc; - /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ - if (DISPLAY_VER(i915) >= 12) - dsc_max_bpc = min_t(u8, 12, max_req_bpc); - else - dsc_max_bpc = min_t(u8, 10, max_req_bpc); + dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915); + + if (!dsc_max_bpc) + return dsc_max_bpc; + + dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, dsc_bpc); @@ -1689,6 +1702,17 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); } +static +u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) +{ + + /* Min DSC Input BPC for ICL+ is 8 */ + if (DISPLAY_VER(i915) >= 11) + return 8; + + return 0; +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1721,10 +1745,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_bpp = pipe_config->pipe_bpp; } - /* Min Input BPC for ICL+ is 8 */ - if (pipe_bpp < 8 * 3) { + if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) { drm_dbg_kms(&dev_priv->drm, - "No DSC support for less than 8bpc\n"); + "Computed BPC less than min supported by source for DSC\n"); return -EINVAL; } From patchwork Fri Jun 16 06:30:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [14/27] drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also From: Ankit Nautiyal X-Patchwork-Id: 542821 Message-Id: <20230616063053.2158108-28-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:37 +0530 For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24. Check this condition for cases where bpc is forced by debugfs flag dsc_force_bpc. If the check fails, then WARN and ignore the debugfs flag. For MST case the pipe_bpp is already computed (hardcoded to be 24), and this check is not required. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 47 ++++++++++++++++--------- 1 file changed, 31 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7f5b39064f13..23869a261f5e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1713,6 +1713,12 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) return 0; } +static +bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp) +{ + return pipe_bpp < intel_dp_dsc_min_src_input_bpc(i915) * 3; +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1724,7 +1730,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - int pipe_bpp; int ret; pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && @@ -1736,27 +1741,37 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) return -EINVAL; - if (intel_dp->force_dsc_bpc && compute_pipe_bpp) { - pipe_bpp = intel_dp->force_dsc_bpc * 3; - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp); - } else if (compute_pipe_bpp) { - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); - } else { - pipe_bpp = pipe_config->pipe_bpp; - } + if (compute_pipe_bpp) { + int pipe_bpp; + int forced_bpp = intel_dp->force_dsc_bpc * 3; - if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) { - drm_dbg_kms(&dev_priv->drm, - "Computed BPC less than min supported by source for DSC\n"); - return -EINVAL; + if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) { + pipe_bpp = forced_bpp; + drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp); + } else { + drm_WARN(&dev_priv->drm, + forced_bpp && !is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp), + "Cannot force dsc bpc:%d, due to dsc bpc limits\n", + intel_dp->force_dsc_bpc); + + pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, + conn_state->max_requested_bpc); + + if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) { + drm_dbg_kms(&dev_priv->drm, + "Computed BPC less than min supported by source for DSC\n"); + return -EINVAL; + } + } + + pipe_config->pipe_bpp = pipe_bpp; } /* - * For now enable DSC for max bpp, max link rate, max lane count. + * For now enable DSC for max link rate, max lane count. * Optimize this later for the minimum possible link rate/lane count * with DSC enabled for the requested mode. */ - pipe_config->pipe_bpp = pipe_bpp; pipe_config->port_clock = limits->max_rate; pipe_config->lane_count = limits->max_lane_count; @@ -1785,7 +1800,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes, pipe_config->output_format, - pipe_bpp, + pipe_config->pipe_bpp, timeslots); if (!dsc_max_compressed_bpp) { drm_dbg_kms(&dev_priv->drm, From patchwork Fri Jun 16 06:30:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [15/27] drm/i915/dp: Avoid left shift of DSC output bpp by 4 From: Ankit Nautiyal X-Patchwork-Id: 542823 Message-Id: <20230616063053.2158108-30-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:39 +0530 To make way for fractional bpp support, avoid left shifting the output_bpp by 4 in helper intel_dp_dsc_get_output_bpp. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 10 +++------- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 23869a261f5e..bbb9635ea316 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -804,11 +804,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); - /* - * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, - * fractional part is 0 - */ - return bits_per_pixel << 4; + return bits_per_pixel; } u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, @@ -1223,7 +1219,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, mode->hdisplay, bigjoiner, output_format, - pipe_bpp, 64) >> 4; + pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1830,7 +1826,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->pipe_bpp); pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_compressed_bpp >> 4, + dsc_max_compressed_bpp, output_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index dff4717edbd0..4895d6242915 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -982,7 +982,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, mode->hdisplay, bigjoiner, INTEL_OUTPUT_FORMAT_RGB, - pipe_bpp, 64) >> 4; + pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, From patchwork Fri Jun 16 06:30:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [16/27] drm/i915/dp: Rename helper to get DSC max pipe_bpp From: Ankit Nautiyal X-Patchwork-Id: 542825 Message-Id: <20230616063053.2158108-32-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:41 +0530 The helper intel_dp_dsc_compute_bpp gives the maximum pipe bpp that is allowed with DSC. Rename the this to reflect that it returns max pipe bpp supported with DSC. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dp.h | 2 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index bbb9635ea316..88120bf0cfeb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1198,7 +1198,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX); /* * Output bpp is stored in 6.4 format so right shift by 4 to get the @@ -1558,7 +1558,7 @@ u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) return 0; } -int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) +int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int i, num_bpc; @@ -1750,8 +1750,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, "Cannot force dsc bpc:%d, due to dsc bpc limits\n", intel_dp->force_dsc_bpc); - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, - conn_state->max_requested_bpc); + pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, + conn_state->max_requested_bpc); if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) { drm_dbg_kms(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 6fd423463f5c..788a577ebe16 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -106,7 +106,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); -int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 4895d6242915..3eb085fbc7c8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -971,7 +971,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX); if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { dsc_max_compressed_bpp = From patchwork Fri Jun 16 06:30:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [17/27] drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp From: Ankit Nautiyal X-Patchwork-Id: 542827 Message-Id: <20230616063053.2158108-34-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:43 +0530 Refactor code to separate functions for computing pipe_bpp and compressed bpp when DSC is involved. This will help to optimize the link configuration for DP later. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 142 +++++++++++++++--------- 1 file changed, 90 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 88120bf0cfeb..4f3d17086598 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1715,6 +1715,80 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp) return pipe_bpp < intel_dp_dsc_min_src_input_bpc(i915) * 3; } +static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots) +{ + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + u16 output_bpp, dsc_max_compressed_bpp = 0; + int pipe_bpp; + + pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc); + if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) { + drm_dbg_kms(&i915->drm, + "Computed BPC less than min supported by source for DSC\n"); + return -EINVAL; + } + /* + * For now enable DSC for max link rate, max lane count. + * Optimize this later for the minimum possible link rate/lane count + * with DSC enabled for the requested mode. + */ + pipe_config->port_clock = limits->max_rate; + pipe_config->lane_count = limits->max_lane_count; + dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915, + pipe_config->port_clock, + pipe_config->lane_count, + adjusted_mode->crtc_clock, + adjusted_mode->crtc_hdisplay, + pipe_config->bigjoiner_pipes, + pipe_config->output_format, + pipe_config->pipe_bpp, + timeslots); + if (!dsc_max_compressed_bpp) { + drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n"); + return -EINVAL; + } + + + output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); + + pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp); + + pipe_config->pipe_bpp = pipe_bpp; + + return 0; +} + +static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits) +{ + /* For eDP use max bpp that can be supported with DSC. */ + int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, + conn_state->max_requested_bpc); + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) { + drm_dbg_kms(&i915->drm, + "Computed BPC less than min supported by source for DSC\n"); + return -EINVAL; + } + pipe_config->port_clock = limits->max_rate; + pipe_config->lane_count = limits->max_lane_count; + pipe_config->dsc.compressed_bpp = + min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, + pipe_bpp); + + pipe_config->pipe_bpp = pipe_bpp; + + return 0; +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1737,6 +1811,12 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) return -EINVAL; + /* + * compute pipe bpp is set to false for DP MST DSC case + * and compressed_bpp is calculated same time once + * vpci timeslots are allocated, because overall bpp + * calculation procedure is bit different for MST case. + */ if (compute_pipe_bpp) { int pipe_bpp; int forced_bpp = intel_dp->force_dsc_bpc * 3; @@ -1749,32 +1829,22 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, forced_bpp && !is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp), "Cannot force dsc bpc:%d, due to dsc bpc limits\n", intel_dp->force_dsc_bpc); - - pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, - conn_state->max_requested_bpc); - - if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) { + if (intel_dp_is_edp(intel_dp)) + ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, + conn_state, limits); + else + ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, + conn_state, limits, timeslots); + if (ret) { drm_dbg_kms(&dev_priv->drm, - "Computed BPC less than min supported by source for DSC\n"); - return -EINVAL; + "No Valid pipe bpp for given mode ret = %d\n", ret); + return ret; } } - - pipe_config->pipe_bpp = pipe_bpp; } - /* - * For now enable DSC for max link rate, max lane count. - * Optimize this later for the minimum possible link rate/lane count - * with DSC enabled for the requested mode. - */ - pipe_config->port_clock = limits->max_rate; - pipe_config->lane_count = limits->max_lane_count; - + /* Calculate Slice count */ if (intel_dp_is_edp(intel_dp)) { - pipe_config->dsc.compressed_bpp = - min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, - pipe_config->pipe_bpp); pipe_config->dsc.slice_count = drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, true); @@ -1784,26 +1854,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } } else { - u16 dsc_max_compressed_bpp = 0; u8 dsc_dp_slice_count; - if (compute_pipe_bpp) { - dsc_max_compressed_bpp = - intel_dp_dsc_get_max_compressed_bpp(dev_priv, - pipe_config->port_clock, - pipe_config->lane_count, - adjusted_mode->crtc_clock, - adjusted_mode->crtc_hdisplay, - pipe_config->bigjoiner_pipes, - pipe_config->output_format, - pipe_config->pipe_bpp, - timeslots); - if (!dsc_max_compressed_bpp) { - drm_dbg_kms(&dev_priv->drm, - "Compressed BPP not supported\n"); - return -EINVAL; - } - } dsc_dp_slice_count = intel_dp_dsc_get_slice_count(intel_dp, adjusted_mode->crtc_clock, @@ -1815,20 +1867,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } - /* - * compute pipe bpp is set to false for DP MST DSC case - * and compressed_bpp is calculated same time once - * vpci timeslots are allocated, because overall bpp - * calculation procedure is bit different for MST case. - */ - if (compute_pipe_bpp) { - u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format, - pipe_config->pipe_bpp); - - pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_compressed_bpp, - output_bpp); - } pipe_config->dsc.slice_count = dsc_dp_slice_count; } /* From patchwork Fri Jun 16 06:30:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [18/27] drm/i915/dp: Get optimal link config to have best compressed bpp From: Ankit Nautiyal X-Patchwork-Id: 542828 Message-Id: <20230616063053.2158108-35-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:44 +0530 Currently, we take the max lane, rate and pipe bpp, to get the maximum compressed bpp possible. We then set the output bpp to this value. This patch provides support to have max bpp, min rate and min lanes, that can support the min compressed bpp. v2: -Avoid ending up with compressed bpp, same as pipe bpp. (Stan) -Fix the checks for limits->max/min_bpp while iterating over list of valid DSC bpcs. (Stan) v3: -Refactor the code to have pipe bpp/compressed bpp computation and slice count calculation separately for different cases. v4: -Separate the pipe_bpp calculation for eDP and DP. v5: -Get rid of magic numbers for max and min bpp, and improve documentation. (Stan). -Use functions for {src_sink}_{min_max}_compressed_bpp (Ville). v6: -Remove lines to set link config to max. v7: -Split the part to separate edp and dp functions for computing DSC BPP into separate patch. Signed-off-by: Ankit Nautiyal Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_dp.c | 243 ++++++++++++++++++++---- 1 file changed, 209 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 4f3d17086598..6cc29eaff63c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1698,6 +1698,183 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); } +static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int compressed_bpp, + const struct drm_display_mode *adjusted_mode) +{ + int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, compressed_bpp); + int link_avail = intel_dp_max_data_rate(link_rate, lane_count); + + return mode_rate <= link_avail; +} + +static int dsc_compute_link_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct link_config_limits *limits, + int pipe_bpp, + u16 compressed_bpp, + int timeslots) +{ + const struct drm_display_mode *adjusted_mode = + &pipe_config->hw.adjusted_mode; + int link_rate, lane_count; + int dsc_max_bpp; + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + int i; + + for (i = 0; i < intel_dp->num_common_rates; i++) { + link_rate = intel_dp_common_rate(intel_dp, i); + if (link_rate < limits->min_rate || link_rate > limits->max_rate) + continue; + + for (lane_count = limits->min_lane_count; + lane_count <= limits->max_lane_count; + lane_count <<= 1) { + dsc_max_bpp = intel_dp_dsc_get_max_compressed_bpp(dev_priv, + link_rate, + lane_count, + adjusted_mode->crtc_clock, + adjusted_mode->crtc_hdisplay, + pipe_config->bigjoiner_pipes, + pipe_config->output_format, + pipe_bpp, timeslots); + /* + * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum + * supported PPS value can be 63.9375 and with the further + * mention that bpp should be programmed double the target bpp + * restricting our target bpp to be 31.9375 at max + */ + if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + dsc_max_bpp = min_t(u16, dsc_max_bpp, 31); + + if (compressed_bpp > dsc_max_bpp) + continue; + + if (!is_dsc_bw_sufficient(link_rate, lane_count, + compressed_bpp, adjusted_mode)) + continue; + + pipe_config->lane_count = lane_count; + pipe_config->port_clock = link_rate; + + return 0; + } + } + + return -EINVAL; +} + +static +u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int bpc) +{ + u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd); + + if (max_bppx16) + return max_bppx16; + /* + * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate + * values as given in spec Table 2-157 DP v2.0 + */ + switch (pipe_config->output_format) { + case INTEL_OUTPUT_FORMAT_RGB: + case INTEL_OUTPUT_FORMAT_YCBCR444: + return (3 * bpc) << 4; + case INTEL_OUTPUT_FORMAT_YCBCR420: + return (3 * (bpc / 2)) << 4; + default: + MISSING_CASE(pipe_config->output_format); + break; + } + + return 0; +} + +static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) +{ + /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ + switch (pipe_config->output_format) { + case INTEL_OUTPUT_FORMAT_RGB: + case INTEL_OUTPUT_FORMAT_YCBCR444: + return 8; + case INTEL_OUTPUT_FORMAT_YCBCR420: + return 6; + default: + MISSING_CASE(pipe_config->output_format); + break; + } + + return 0; +} + +static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int bpc) +{ + return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp, + pipe_config, bpc) >> 4; +} + +static int dsc_src_min_compressed_bpp(void) +{ + /* Min Compressed bpp supported by source is 8 */ + return 8; +} + +static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + /* + * Max Compressed bpp for Gen 13+ is 27bpp. + * For earlier platform is 23bpp. (Bspec:49259). + */ + if (DISPLAY_VER(i915) <= 12) + return 23; + else + return 27; +} + +static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct link_config_limits *limits, + int pipe_bpp, + int timeslots) +{ + u16 compressed_bpp; + int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; + int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; + int ret; + + dsc_src_min_bpp = dsc_src_min_compressed_bpp(); + dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config); + dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); + + dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); + dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3); + dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; + + /* Compressed BPP should be less than the Input DSC bpp */ + dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); + + for (compressed_bpp = dsc_max_bpp; + compressed_bpp >= dsc_min_bpp; + compressed_bpp--) { + ret = dsc_compute_link_config(intel_dp, + pipe_config, + limits, + pipe_bpp, + compressed_bpp, + timeslots); + if (ret == 0) { + pipe_config->dsc.compressed_bpp = compressed_bpp; + return 0; + } + } + + return -EINVAL; +} + static u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) { @@ -1721,46 +1898,44 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct link_config_limits *limits, int timeslots) { - const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; struct drm_i915_private *i915 = dp_to_i915(intel_dp); - u16 output_bpp, dsc_max_compressed_bpp = 0; - int pipe_bpp; - - pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc); - if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) { - drm_dbg_kms(&i915->drm, - "Computed BPC less than min supported by source for DSC\n"); - return -EINVAL; - } - /* - * For now enable DSC for max link rate, max lane count. - * Optimize this later for the minimum possible link rate/lane count - * with DSC enabled for the requested mode. - */ - pipe_config->port_clock = limits->max_rate; - pipe_config->lane_count = limits->max_lane_count; - dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915, - pipe_config->port_clock, - pipe_config->lane_count, - adjusted_mode->crtc_clock, - adjusted_mode->crtc_hdisplay, - pipe_config->bigjoiner_pipes, - pipe_config->output_format, - pipe_config->pipe_bpp, - timeslots); - if (!dsc_max_compressed_bpp) { - drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n"); + u8 dsc_bpc[3] = {0}; + u8 dsc_max_bpc, dsc_max_bpp; + u8 dsc_min_bpc, dsc_min_bpp; + u8 max_req_bpc = conn_state->max_requested_bpc; + int i, bpp, ret; + int num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + + dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915); + if (!dsc_max_bpc) return -EINVAL; - } + dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); + dsc_max_bpp = min(dsc_max_bpc * 3, limits->max_bpp); - output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); - - pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp); + dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915); + dsc_min_bpp = max(dsc_min_bpc * 3, limits->min_bpp); - pipe_config->pipe_bpp = pipe_bpp; + /* + * Get the maximum DSC bpc that will be supported by any valid + * link configuration and compressed bpp. + */ + for (i = 0; i < num_bpc; i++) { + bpp = dsc_bpc[i] * 3; + if (bpp < dsc_min_bpp) + break; + if (bpp > dsc_max_bpp) + continue; + ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, + limits, bpp, timeslots); + if (ret == 0) { + pipe_config->pipe_bpp = bpp; + return 0; + } + } - return 0; + return -EINVAL; } static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, From patchwork Fri Jun 16 06:30:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [19/27] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info From: Ankit Nautiyal X-Patchwork-Id: 542829 Message-Id: <20230616063053.2158108-36-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:45 +0530 From: Stanislav Lisovskiy Currently we seem to be using wrong DPCD register for reading compressed bpps, reading min/max input bpc instead of compressed bpp. Fix that, so that we now apply min/max compressed bpp limitations we get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD register DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH. This might also allow us to get rid of an ugly compressed bpp recalculation, which we had to add to make some MST hubs usable. v2: - Fix operator precedence v3: - Added debug info about compressed bpps v4: - Don't try to intersect Sink input bpp and compressed bpps. v5: - Decrease step while looking for suitable compressed bpp to accommodate. v6: - Use helper for getting min and max compressed_bpp (Ankit) Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 12 +++--- drivers/gpu/drm/i915/display/intel_dp.h | 4 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 43 ++++++++------------- 3 files changed, 26 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6cc29eaff63c..b18c46e21f55 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1790,7 +1790,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp, return 0; } -static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) +int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) { /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ switch (pipe_config->output_format) { @@ -1807,9 +1807,9 @@ static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) return 0; } -static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, - int bpc) +int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int bpc) { return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp, pipe_config, bpc) >> 4; @@ -1847,11 +1847,11 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, int ret; dsc_src_min_bpp = dsc_src_min_compressed_bpp(); - dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config); + dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config); dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); - dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3); + dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3); dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; /* Compressed BPP should be less than the Input DSC bpp */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 788a577ebe16..f29e48028f39 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -114,6 +114,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, enum intel_output_format output_format, u32 pipe_bpp, u32 timeslots); +int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config); +int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int bpc); u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, int mode_hdisplay, bool bigjoiner); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 3eb085fbc7c8..0df930d605ed 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -101,6 +101,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, crtc_state->lane_count); } + drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n", + min_bpp, max_bpp); + for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); @@ -194,8 +197,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, u8 dsc_bpc[3] = {0}; int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; u8 dsc_max_bpc; - bool need_timeslot_recalc = false; - u32 last_compressed_bpp; + int min_compressed_bpp, max_compressed_bpp; /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ if (DISPLAY_VER(i915) >= 12) @@ -231,34 +233,21 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, if (max_bpp > sink_max_bpp) max_bpp = sink_max_bpp; - slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp, - min_bpp, limits, - conn_state, 2 * 3, true); - - if (slots < 0) - return slots; - - last_compressed_bpp = crtc_state->dsc.compressed_bpp; + max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp, crtc_state, max_bpp / 3); + min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state); + drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n", + min_compressed_bpp, max_compressed_bpp); - crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, - last_compressed_bpp, - crtc_state->pipe_bpp); + /* Align compressed bpps according to our own constraints */ + max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp, crtc_state->pipe_bpp); + min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp, crtc_state->pipe_bpp); - if (crtc_state->dsc.compressed_bpp != last_compressed_bpp) - need_timeslot_recalc = true; + slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp, + min_compressed_bpp, limits, + conn_state, 1, true); - /* - * Apparently some MST hubs dislike if vcpi slots are not matching precisely - * the actual compressed bpp we use. - */ - if (need_timeslot_recalc) { - slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, - crtc_state->dsc.compressed_bpp, - crtc_state->dsc.compressed_bpp, - limits, conn_state, 2 * 3, true); - if (slots < 0) - return slots; - } + if (slots < 0) + return slots; intel_link_compute_m_n(crtc_state->dsc.compressed_bpp, crtc_state->lane_count, From patchwork Fri Jun 16 06:30:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [20/27] drm/i915/display: Store compressed bpp in U6.4 format From: Ankit Nautiyal X-Patchwork-Id: 542830 Message-Id: <20230616063053.2158108-37-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:46 +0530 DSC parameter bits_per_pixel is stored in U6.4 format. The 4 bits represent the fractional part of the bpp. Currently we use compressed_bpp member of dsc structure to store only the integral part of the bits_per_pixel. To store the full bits_per_pixel along with the fractional part, compressed_bpp is changed to store bpp in U6.4 formats. Intergral part is retrieved by simply right shifting the member compressed_bpp by 4. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++---- drivers/gpu/drm/i915/display/intel_audio.c | 2 +- drivers/gpu/drm/i915/display/intel_bios.c | 2 +- .../drm/i915/display/intel_display_types.h | 16 ++++++++++++- drivers/gpu/drm/i915/display/intel_dp.c | 23 +++++++++++-------- drivers/gpu/drm/i915/display/intel_vdsc.c | 4 ++-- 6 files changed, 37 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 59a2a289d9be..d20bf3ab7212 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder, int bpp; if (crtc_state->dsc.compression_enable) - bpp = crtc_state->dsc.compressed_bpp; + bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp); else bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); @@ -859,7 +859,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, * compressed and non-compressed bpp. */ if (crtc_state->dsc.compression_enable) { - mul = crtc_state->dsc.compressed_bpp; + mul = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp); div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); } @@ -883,7 +883,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, int bpp, line_time_us, byte_clk_period_ns; if (crtc_state->dsc.compression_enable) - bpp = crtc_state->dsc.compressed_bpp; + bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp); else bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); @@ -1450,8 +1450,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - if (pipe_config->dsc.compressed_bpp) { - int div = pipe_config->dsc.compressed_bpp; + if (dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)) { + int div = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp); int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); adjusted_mode->crtc_htotal = diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 3d9c9b4f27f8..93969b63cdd8 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; h_total = crtc_state->hw.adjusted_mode.crtc_htotal; pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; - vdsc_bpp = crtc_state->dsc.compressed_bpp; + vdsc_bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp); cdclk = i915->display.cdclk.hw.cdclk; /* fec= 0.972261, using rounding multiplier of 1000000 */ fec_coeff = 972261; diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 34a397adbd6b..2290a55227c6 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -3504,7 +3504,7 @@ static void fill_dsc(struct intel_crtc_state *crtc_state, crtc_state->pipe_bpp = bpc * 3; crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, - VBT_DSC_MAX_BPP(dsc->max_bpp)); + VBT_DSC_MAX_BPP(dsc->max_bpp)) << 4; /* * FIXME: This is ugly, and slice count should take DSC engine diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 731f2ec04d5c..f749dc4e70df 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1353,7 +1353,7 @@ struct intel_crtc_state { struct { bool compression_enable; bool dsc_split; - u16 compressed_bpp; + u16 compressed_bpp; /* U6.4 format (first 4 bits for fractional part) */ u8 slice_count; struct drm_dsc_config config; } dsc; @@ -2108,4 +2108,18 @@ to_intel_frontbuffer(struct drm_framebuffer *fb) return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; } +/* Returns integral part of the compressed bpp given in U6.4 format */ +static inline int +dsc_integral_compressed_bpp(u16 compressed_bpp) +{ + return compressed_bpp >> 4; +} + +/* Returns fractional part of the compressed bpp given in U6.4 format */ +static inline int +dsc_fractional_compressed_bpp(u16 compressed_bpp) +{ + return ((compressed_bpp & 0xF) * 10000 / 16); +} + #endif /* __INTEL_DISPLAY_TYPES_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b18c46e21f55..8911b012a150 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1867,7 +1867,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, compressed_bpp, timeslots); if (ret == 0) { - pipe_config->dsc.compressed_bpp = compressed_bpp; + pipe_config->dsc.compressed_bpp = compressed_bpp << 4; return 0; } } @@ -1959,7 +1959,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, pipe_bpp); - pipe_config->pipe_bpp = pipe_bpp; + pipe_config->pipe_bpp = pipe_bpp << 4; return 0; } @@ -2056,17 +2056,19 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (ret < 0) { drm_dbg_kms(&dev_priv->drm, "Cannot compute valid DSC parameters for Input Bpp = %d " - "Compressed BPP = %d\n", + "Compressed BPP = %d.%d\n", pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp); + dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp), + dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp)); return ret; } pipe_config->dsc.compression_enable = true; drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " - "Compressed Bpp = %d Slice Count = %d\n", + "Compressed Bpp = %d.%d Slice Count = %d\n", pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp, + dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp), + dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp), pipe_config->dsc.slice_count); return 0; @@ -2145,15 +2147,16 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, if (pipe_config->dsc.compression_enable) { drm_dbg_kms(&i915->drm, - "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", + "DP lane count %d clock %d Input bpp %d Compressed bpp %d.%d\n", pipe_config->lane_count, pipe_config->port_clock, pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp); + dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp), + dsc_fractional_compressed_bpp(pipe_config->dsc.compressed_bpp)); drm_dbg_kms(&i915->drm, "DP link rate required %i available %i\n", intel_dp_link_required(adjusted_mode->crtc_clock, - pipe_config->dsc.compressed_bpp), + dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp)), intel_dp_max_data_rate(pipe_config->port_clock, pipe_config->lane_count)); } else { @@ -2585,7 +2588,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_dp_limited_color_range(pipe_config, conn_state); if (pipe_config->dsc.compression_enable) - link_bpp = pipe_config->dsc.compressed_bpp; + link_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp); else link_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_config->pipe_bpp); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 11227491834e..5c30150c54df 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -155,7 +155,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; - u16 compressed_bpp = pipe_config->dsc.compressed_bpp; + u16 compressed_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp); int err; int ret; @@ -970,7 +970,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) if (pps0 & DSC_NATIVE_420_ENABLE) vdsc_cfg->bits_per_pixel >>= 1; - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel; out: intel_display_power_put(dev_priv, power_domain, wakeref); } From patchwork Fri Jun 16 06:30:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [21/27] drm/i915/display: Consider fractional vdsc bpp while computing m_n values From: Ankit Nautiyal X-Patchwork-Id: 542832 Message-Id: <20230616063053.2158108-38-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:47 +0530 MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate this precision while computing m_n values. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- 5 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d8533603ad05..9b4980f5cb59 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2380,10 +2380,14 @@ void intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, - bool fec_enable) + bool fec_enable, + bool is_dsc_fractional_bpp) { u32 data_clock = bits_per_pixel * pixel_clock; + if (is_dsc_fractional_bpp) + data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16); + if (fec_enable) data_clock = intel_dp_mode_to_fec_clock(data_clock); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index c744c021af23..82282a800ad7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state, void intel_link_compute_m_n(u16 bpp, int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, - bool fec_enable); + bool fec_enable, bool is_dsc_fractional_bpp); u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, u32 pixel_format, u64 modifier); enum drm_mode_status diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8911b012a150..2aa9f7588dd0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2442,7 +2442,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock, pipe_config->port_clock, &pipe_config->dp_m2_n2, - pipe_config->fec_enable); + pipe_config->fec_enable, false); /* FIXME: abstract this better */ if (pipe_config->splitter.enable) @@ -2588,7 +2588,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_dp_limited_color_range(pipe_config, conn_state); if (pipe_config->dsc.compression_enable) - link_bpp = dsc_integral_compressed_bpp(pipe_config->dsc.compressed_bpp); + link_bpp = pipe_config->dsc.compressed_bpp; else link_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_config->pipe_bpp); @@ -2620,7 +2620,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, pipe_config->port_clock, &pipe_config->dp_m_n, - pipe_config->fec_enable); + pipe_config->fec_enable, + pipe_config->dsc.compression_enable); /* FIXME: abstract this better */ if (pipe_config->splitter.enable) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 0df930d605ed..43237d51cf06 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -174,7 +174,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, crtc_state->port_clock, &crtc_state->dp_m_n, - crtc_state->fec_enable); + crtc_state->fec_enable, + false); crtc_state->dp_m_n.tu = slots; return 0; @@ -254,7 +255,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, crtc_state->port_clock, &crtc_state->dp_m_n, - crtc_state->fec_enable); + crtc_state->fec_enable, + crtc_state->dsc.compression_enable); crtc_state->dp_m_n.tu = slots; return 0; diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index e12b46a84fa1..15fddabf7c2e 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc, pipe_config->fdi_lanes = lane; intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, - link_bw, &pipe_config->fdi_m_n, false); + link_bw, &pipe_config->fdi_m_n, false, false); ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config); if (ret == -EDEADLK) From patchwork Fri Jun 16 06:30:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [22/27] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data From: Ankit Nautiyal X-Patchwork-Id: 542831 Message-Id: <20230616063053.2158108-39-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:48 +0530 MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate the precision during calculation of transfer unit data for hblank_early calculation. v2: -Fixed tu_data calculation while dealing with U6.4 format. (Stan) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_audio.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 93969b63cdd8..bbd99e2fb399 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -521,14 +521,14 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, unsigned int link_clks_available, link_clks_required; unsigned int tu_data, tu_line, link_clks_active; unsigned int h_active, h_total, hblank_delta, pixel_clk; - unsigned int fec_coeff, cdclk, vdsc_bpp; + unsigned int fec_coeff, cdclk, vdsc_bppx16; unsigned int link_clk, lanes; unsigned int hblank_rise; h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; h_total = crtc_state->hw.adjusted_mode.crtc_htotal; pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; - vdsc_bpp = dsc_integral_compressed_bpp(crtc_state->dsc.compressed_bpp); + vdsc_bppx16 = crtc_state->dsc.compressed_bpp; cdclk = i915->display.cdclk.hw.cdclk; /* fec= 0.972261, using rounding multiplier of 1000000 */ fec_coeff = 972261; @@ -536,10 +536,10 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, lanes = crtc_state->lane_count; drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :" - "lanes = %u vdsc_bpp = %u cdclk = %u\n", - h_active, link_clk, lanes, vdsc_bpp, cdclk); + "lanes = %u vdsc_bppx16 = %u cdclk = %u\n", + h_active, link_clk, lanes, vdsc_bppx16, cdclk); - if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) + if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) return 0; link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; @@ -551,8 +551,8 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), mul_u32_u32(link_clk, cdclk)); - tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000), - mul_u32_u32(link_clk * lanes, fec_coeff)); + tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), + mul_u32_u32(link_clk * lanes * 16, fec_coeff)); tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), mul_u32_u32(64 * pixel_clk, 1000000)); link_clks_active = (tu_line - 1) * 64 + tu_data; From patchwork Fri Jun 16 06:30:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [23/27] drm/display/dp: Add helper function to get DSC bpp prescision From: Ankit Nautiyal X-Patchwork-Id: 542835 Message-Id: <20230616063053.2158108-40-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:49 +0530 Add helper to get the DSC bits_per_pixel precision for the DP sink. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++ include/drm/display/drm_dp_helper.h | 1 + 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index 16565a0a5da6..db3288af4032 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, } EXPORT_SYMBOL(drm_dp_read_desc); +/** + * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment + * @dsc_dpcd: DSC capabilities from DPCD + * + * Returns the bpp precision supported by the DP sink. + */ +u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; + + switch (bpp_increment_dpcd) { + case DP_DSC_BITS_PER_PIXEL_1_16: + return 16; + case DP_DSC_BITS_PER_PIXEL_1_8: + return 8; + case DP_DSC_BITS_PER_PIXEL_1_4: + return 4; + case DP_DSC_BITS_PER_PIXEL_1_2: + return 2; + case DP_DSC_BITS_PER_PIXEL_1_1: + return 1; + } + + return 0; +} +EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr); + /** * drm_dp_dsc_sink_max_slice_count() - Get the max slice count * supported by the DSC sink. diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index 86f24a759268..ba0514f0b032 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) } /* DP/eDP DSC support */ +u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], bool is_edp); u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); From patchwork Fri Jun 16 06:30:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [24/27] drm/i915/dsc/mtl: Add support for fractional bpp From: Ankit Nautiyal X-Patchwork-Id: 542833 Message-Id: <20230616063053.2158108-41-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:50 +0530 From: Vandita Kulkarni Consider the fractional bpp while reading the qp values. Signed-off-by: Vandita Kulkarni Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_qp_tables.c | 3 --- drivers/gpu/drm/i915/display/intel_vdsc.c | 13 ++++++++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c index 6e86c0971d24..487721e6c2f1 100644 --- a/drivers/gpu/drm/i915/display/intel_qp_tables.c +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c @@ -30,9 +30,6 @@ * These qp tables are as per the C model * and it has the rows pointing to bpps which increment * in steps of 0.5 - * We do not support fractional bpps as of today, - * hence we would skip the fractional bpps during - * our references for qp calclulations. */ static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 5c30150c54df..cfd1c0ce0754 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -57,6 +57,7 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) { int bpc = vdsc_cfg->bits_per_component; int bpp = vdsc_cfg->bits_per_pixel >> 4; + int fractional_bits = vdsc_cfg->bits_per_pixel & 0xf; static const s8 ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 }; @@ -97,7 +98,14 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier; vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier; - bpp_i = (2 * (bpp - 6)); + /* + * QP table rows have values in increment of 0.5. + * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1, + * and so on. + * 0.5 represented as 0x8 in U6.4 format. + */ + bpp_i = ((bpp - 6) + (fractional_bits < 0x8 ? 0 : 1)); + for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { u8 range_bpg_offset; @@ -186,8 +194,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) /* Gen 11 does not support VBR */ vdsc_cfg->vbr_enable = false; - /* Gen 11 only supports integral values of bpp */ - vdsc_cfg->bits_per_pixel = compressed_bpp << 4; + vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp; /* * According to DSC 1.2 specs in Section 4.1 if native_420 is set: From patchwork Fri Jun 16 06:30:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [25/27] drm/i915/dp: Iterate over output bpp with fractional step size From: Ankit Nautiyal X-Patchwork-Id: 542834 Message-Id: <20230616063053.2158108-42-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:51 +0530 This patch adds support to iterate over compressed output bpp as per the fractional step, supported by DP sink. v2: -Avoid ending up with compressed bpp, same as pipe bpp. (Stan) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 32 ++++++++++++++++--------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2aa9f7588dd0..d850094ca466 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1698,10 +1698,12 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); } -static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int compressed_bpp, +static bool is_dsc_bw_sufficient(int link_rate, int lane_count, int compressed_bppx16, const struct drm_display_mode *adjusted_mode) { - int mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, compressed_bpp); + int mode_rate = DIV_ROUND_UP(intel_dp_link_required(adjusted_mode->crtc_clock, + compressed_bppx16), 16); + int link_avail = intel_dp_max_data_rate(link_rate, lane_count); return mode_rate <= link_avail; @@ -1711,7 +1713,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, int pipe_bpp, - u16 compressed_bpp, + u16 compressed_bppx16, int timeslots) { const struct drm_display_mode *adjusted_mode = @@ -1746,11 +1748,11 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) dsc_max_bpp = min_t(u16, dsc_max_bpp, 31); - if (compressed_bpp > dsc_max_bpp) + if (compressed_bppx16 > dsc_max_bpp << 16) continue; if (!is_dsc_bw_sufficient(link_rate, lane_count, - compressed_bpp, adjusted_mode)) + compressed_bppx16, adjusted_mode)) continue; pipe_config->lane_count = lane_count; @@ -1841,9 +1843,12 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, int pipe_bpp, int timeslots) { - u16 compressed_bpp; + u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd); + struct drm_i915_private *i915 = dp_to_i915(intel_dp); int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; + u16 compressed_bppx16; + u8 bppx16_step; int ret; dsc_src_min_bpp = dsc_src_min_compressed_bpp(); @@ -1857,17 +1862,22 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, /* Compressed BPP should be less than the Input DSC bpp */ dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); - for (compressed_bpp = dsc_max_bpp; - compressed_bpp >= dsc_min_bpp; - compressed_bpp--) { + if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1) + bppx16_step = 16; + else + bppx16_step = 16 / bppx16_incr; + + for (compressed_bppx16 = dsc_max_bpp << 4; + compressed_bppx16 >= dsc_min_bpp << 4; + compressed_bppx16 -= bppx16_step) { ret = dsc_compute_link_config(intel_dp, pipe_config, limits, pipe_bpp, - compressed_bpp, + compressed_bppx16, timeslots); if (ret == 0) { - pipe_config->dsc.compressed_bpp = compressed_bpp << 4; + pipe_config->dsc.compressed_bpp = compressed_bppx16; return 0; } } From patchwork Fri Jun 16 06:30:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [26/27] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp From: Ankit Nautiyal X-Patchwork-Id: 542836 Message-Id: <20230616063053.2158108-43-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:52 +0530 From: Swati Sharma DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show to depict sink's precision. Also, new debugfs entry is created to enforce fractional bpp. If Force_DSC_Fractional_BPP_en is set then while iterating over output bpp with fractional step size we will continue if output_bpp is computed as integer. With this approach, we will be able to validate DSC with fractional bpp. Signed-off-by: Swati Sharma Signed-off-by: Ankit Nautiyal --- .../drm/i915/display/intel_display_debugfs.c | 82 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 1 + 2 files changed, 83 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 165e2c7e3126..20f0d989f396 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1242,6 +1242,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) DP_DSC_YCbCr420_Native)), str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, DP_DSC_YCbCr444))); + seq_printf(m, "DSC_Sink_BPP_Precision: %d\n", + drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd)); seq_printf(m, "Force_DSC_Enable: %s\n", str_yes_no(intel_dp->force_dsc_en)); if (!intel_dp_is_edp(intel_dp)) @@ -1434,6 +1436,83 @@ static const struct file_operations i915_dsc_output_format_fops = { .write = i915_dsc_output_format_write }; +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + struct drm_device *dev = connector->dev; + struct drm_crtc *crtc; + struct intel_dp *intel_dp; + struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); + int ret; + + if (!encoder) + return -ENODEV; + + ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex); + if (ret) + return ret; + + crtc = connector->state->crtc; + if (connector->status != connector_status_connected || !crtc) { + ret = -ENODEV; + goto out; + } + + intel_dp = intel_attached_dp(to_intel_connector(connector)); + seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n", + str_yes_no(intel_dp->force_dsc_fractional_bpp_en)); + +out: drm_modeset_unlock(&dev->mode_config.connection_mutex); + + return ret; +} + +static ssize_t i915_dsc_fractional_bpp_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct drm_connector *connector = + ((struct seq_file *)file->private_data)->private; + struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + bool dsc_fractional_bpp_enable = false; + int ret; + + if (len == 0) + return 0; + + drm_dbg(&i915->drm, + "Copied %zu bytes from user to force fractional bpp for DSC\n", len); + + ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable); + if (ret < 0) + return ret; + + drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n", + (dsc_fractional_bpp_enable) ? "true" : "false"); + intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable; + + *offp += len; + + return len; +} + +static int i915_dsc_fractional_bpp_open(struct inode *inode, + struct file *file) +{ + return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private); +} + +static const struct file_operations i915_dsc_fractional_bpp_fops = { + .owner = THIS_MODULE, + .open = i915_dsc_fractional_bpp_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = i915_dsc_fractional_bpp_write +}; + /* * Returns the Current CRTC's bpc. * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc @@ -1511,6 +1590,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector) debugfs_create_file("i915_dsc_output_format", 0644, root, connector, &i915_dsc_output_format_fops); + + debugfs_create_file("i915_dsc_fractional_bpp", 0644, root, + connector, &i915_dsc_fractional_bpp_fops); } if (connector->connector_type == DRM_MODE_CONNECTOR_DSI || diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index f749dc4e70df..5f21ee5bda21 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1796,6 +1796,7 @@ struct intel_dp { /* Display stream compression testing */ bool force_dsc_en; int force_dsc_output_format; + bool force_dsc_fractional_bpp_en; int force_dsc_bpc; bool hobl_failed; From patchwork Fri Jun 16 06:30:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [27/27] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs From: Ankit Nautiyal X-Patchwork-Id: 542837 Message-Id: <20230616063053.2158108-44-ankit.k.nautiyal@intel.com> To: intel-gfx-trybot@lists.freedesktop.org Date: Fri, 16 Jun 2023 12:00:53 +0530 From: Swati Sharma If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff compressed bpp is fractional. Continue if we computed compressed bpp is computed as integer. Signed-off-by: Swati Sharma --- drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d850094ca466..5ca89d8b6b37 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1870,6 +1870,9 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, for (compressed_bppx16 = dsc_max_bpp << 4; compressed_bppx16 >= dsc_min_bpp << 4; compressed_bppx16 -= bppx16_step) { + if (intel_dp->force_dsc_fractional_bpp_en && + !dsc_fractional_compressed_bpp(compressed_bppx16)) + continue; ret = dsc_compute_link_config(intel_dp, pipe_config, limits, @@ -1878,6 +1881,11 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, timeslots); if (ret == 0) { pipe_config->dsc.compressed_bpp = compressed_bppx16; + + if (intel_dp->force_dsc_fractional_bpp_en && + dsc_fractional_compressed_bpp(compressed_bppx16)) + drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n"); + return 0; } }